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PI7C21P100
2-PORT PCI-X BRIDGE
REVISION 1.06
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LIFE SUPPORT POLICY Pericom Semiconductor Corporation's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC. 1) Life support devices or system are devices or systems which: a) Are intended for surgical implant into the body or b) Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2) A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. All other trademarks are of their respective companies.
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
REVISION HISTORY
Date 12/04/03 12/11/03 01/22/04 02/02/04 03/15/04 09/13/04 Revision Number 1.00 1.01 1.02 1.03 1.04 1.05 Description First Release of Data Sheet Minor text corrections made. Addition of Features section as well as a couple of tables. Text corrections. Corrected Device ID Register bits 11:0 descriptions. Corrected pin designation for P_RST to E22 in section 3.2.1 Corrected Cin max in section 10.2 (DC specifications) from 0.8pF to 8pF Added power consumption data in Section 10.4 Corrected pin description for TEST_CE0 (Y23) in section 3.2.8 Correct package outline drawing in section 11 Added Pb-free & Green ordering information in section 12
04/13/05 06/10/05
1.051 1.06
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
TABLE OF CONTENTS
1 2 3 DESCRIPTION................................................................................................................................... 9 FEATURES ......................................................................................................................................... 9 SIGNAL DEFINITIONS.................................................................................................................. 10 3.1 SIGNAL TYPES ....................................................................................................................... 10 3.2 SIGNALS .................................................................................................................................. 10 3.2.1 PRIMARY BUS INTERFACE SIGNALS............................................................................... 10 3.2.2 PRIMARY BUS INTERFACE SIGNALS - 64-BIT EXTENSION.......................................... 12 3.2.3 SECONDARY BUS INTERFACE SIGNALS......................................................................... 13 3.2.4 SECONDARY BUS INTERFACE SIGNALS - 64-BIT EXTENSION.................................... 14 3.2.5 CLOCK SIGNALS................................................................................................................. 15 3.2.6 STRAPPING PINS AND MISCELLANEOUS SIGNALS ...................................................... 16 3.2.7 JTAG BOUNDARY SCAN AND TEST SIGNALS ................................................................. 17 3.2.8 TEST SIGNALS..................................................................................................................... 18 3.2.9 POWER AND GROUND SIGNALS...................................................................................... 18 3.3 PIN LIST ................................................................................................................................... 19 4 PCI BUS OPERATION.................................................................................................................... 22 4.1 TYPES OF TRANSACTIONS.................................................................................................. 22 4.2 WRITE TRANSACTIONS ....................................................................................................... 23 4.2.1 MEMORY WRITE TRANSACTIONS .................................................................................... 23
4.2.1.1 4.2.1.2 4.2.1.3 4.2.1.4 PCI-X TO PCI-X ....................................................................................................................... 24 PCI TO PCI................................................................................................................................ 24 PCI TO PCI-X............................................................................................................................ 24 PCI-X TO PCI............................................................................................................................ 25
4.2.2 DELAYED/SPLIT WRITE TRANSACTIONS........................................................................ 25 4.2.3 IMMEDIATE WRITE TRANSACTIONS ............................................................................... 25 4.3 READ TRANSACTIONS ......................................................................................................... 25 4.3.1 MEMORY READ TRANSACTIONS...................................................................................... 26
4.3.1.1 4.3.1.2 4.3.1.3 4.3.1.4 PCI-X TO PCI-X ....................................................................................................................... 26 PCI TO PCI................................................................................................................................ 26 PCI TO PCI-X............................................................................................................................ 26 PCI-X TO PCI............................................................................................................................ 27
4.3.2 4.3.3 4.3.4 4.3.5
I/O READ.............................................................................................................................. 27 CONFIGURATION READ ................................................................................................... 27
TYPE 1 CONFIGURATION READ ......................................................................................... 27 TYPE 0 CONFIGURATION READ ......................................................................................... 27
4.3.3.1 4.3.3.2
NON-PREFETCHABLE AND DWORD READS.................................................................. 28 PREFETCHABLE READS.................................................................................................... 28
PCI-X TO PCI-X AND PCI-X TO PCI .................................................................................... 28 PCI TO PCI................................................................................................................................ 28 PCI TO PCI-X............................................................................................................................ 29
4.3.5.1 4.3.5.2 4.3.5.3
4.3.6 DYNAMIC PREFETCH (CONVENTIONAL PCI MODE ONLY) ........................................ 29 4.4 CONFIGURATION TRANSACTIONS ................................................................................... 29 4.4.1 TYPE 0 ACCESS TO PI7C21P100....................................................................................... 30 4.4.2 TYPE 1 TO TYPE 0 CONVERSION ..................................................................................... 30 4.4.3 TYPE 1 TO TYPE 1 FORWARDING.................................................................................... 31 4.4.4 SPECIAL CYCLES ............................................................................................................... 32 5 TRANSACTION ORDERING ........................................................................................................ 32 5.1 5.2 6 GENERAL ORDERING GUIDELINES................................................................................... 33 ORDERING RULES................................................................................................................. 33
CLOCKS............................................................................................................................................ 34 Page 5 of 77 June 10, 2005 Revision 1.06
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION 6.1 PRIMARY AND SECONDARY CLOCK INPUTS ................................................................. 34 6.2 CLOCK JITTER........................................................................................................................ 34 6.3 MODE AND CLOCK FREQUENCY DETERMINATION ..................................................... 34 6.3.1 PRIMARY BUS ..................................................................................................................... 34 6.3.2 SECONDARY BUS ............................................................................................................... 35 6.3.3 CLOCK STABILITY.............................................................................................................. 36 6.3.4 DRIVER IMPEDANCE SELECTION................................................................................... 36 7 RESET ............................................................................................................................................... 36 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 8.1 PRIMARY INTERFACE RESET ............................................................................................. 37 SECONDARY INTERFACE RESET ....................................................................................... 37 BUS PARKING & BUS WIDTH DETERMINATION............................................................. 38 SECONDARY DEVICE MASKING........................................................................................ 38 ADDRESS PARITY ERRORS ................................................................................................. 39 OPTIONAL BASE ADDRESS REGISTER ............................................................................. 39 OPTIONAL CONFIGURATION ACCESS FROM THE SECONDARY BUS........................ 39 SHORT TERM CACHING ....................................................................................................... 40 CONFIGURATION REGISTER SPACE MAP........................................................................ 41
8.1.1.1 SIGNAL TYPE DEFINITION................................................................................................... 42
CONFIGURATION REGISTERS .................................................................................................. 41
8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 8.1.9 8.1.10 8.1.11 8.1.12 8.1.13 8.1.14 8.1.15 8.1.16 8.1.17 8.1.18 8.1.19 8.1.20 8.1.21 8.1.22 8.1.23 8.1.24 8.1.25 8.1.26 8.1.27 8.1.28 8.1.29 8.1.30 8.1.31 8.1.32 8.1.33 8.1.34 8.1.35
VENDOR ID REGISTER - OFFSET 00h............................................................................. 42 DEVICE ID REGISTER - OFFSET 00h .............................................................................. 42 COMMAND REGISTER - OFFSET 04h.............................................................................. 42 PRIMARY STATUS REGISTER - OFFSET 04h .................................................................. 43 REVISION ID REGISTER - OFFSET 08h ........................................................................... 44 CLASS CODE REGISTER - OFFSET 08h........................................................................... 44 CACHE LINE SIZE REGISTER - OFFSET 0Ch ................................................................. 44 PRIMARY LATENCY TIMER - OFFSET 0Ch ..................................................................... 44 HEADER TYPE REGISTER - OFFSET 0Ch................................................................... 44 BIST REGISTER - OFFSET 0Ch .................................................................................... 44 LOWER MEMORY BASE ADDRESS REGISTER - OFFSET 10h .................................. 45 UPPER MEMORY BASE ADDRESS REGISTER - OFFSET 14h................................... 45 PRIMARY BUS NUMBER REGISTER - OFFSET 18h ................................................... 45 SECONDARY BUS NUMBER REGISTER - OFFSET 18h ............................................. 45 SUBORDINATE BUS NUMBER REGISTER - OFFSET 18h ......................................... 45 SECONDARY LATENCY TIMER REGISTER - OFFSET 18h ........................................ 45 I/O BASE ADDRESS REGISTER - OFFSET 1Ch........................................................... 46 I/O LIMIT REGISTER - OFFSET 1Ch............................................................................ 46 SECONDARY STATUS REGISTER - OFFSET 1Ch ....................................................... 46 MEMORY BASE REGISTER - OFFSET 20h .................................................................. 47 MEMORY LIMIT REGISTER - OFFSET 20h ................................................................. 47 PREFETCHABLE MEMORY BASE REGISTER - OFFSET 24h.................................... 47 PREFETCHABLE MEMORY LIMIT REGISTER - OFFSET 24h................................... 47 PREFETCHABLE BASE UPPER 32-BIT REGISTER - OFFSET 28h............................ 47 PREFETCHABLE LIMIT UPPER 32-BIT REGISTER - OFFSET 2Ch.......................... 48 I/O BASE UPPER 16-BIT REGISTER - OFFSET 30h.................................................... 48 I/O LIMIT UPPER 16-BIT REGISTER - OFFSET 30h .................................................. 48 CAPABILITY POINTER - OFFSET 34h ......................................................................... 48 EXPANSION ROM BASE ADDRESS REGISTER - OFFSET 38h .................................. 48 INTERRUPT LINE REGISTER - OFFSET 3Ch.............................................................. 48 INTERRUPT PIN REGISTER - OFFSET 3Ch ................................................................ 48 BRIDGE CONTROL REGISTER - OFFSET 3Ch ........................................................... 49 PRIMARY DATA BUFFERING CONTROL REGISTER - OFFSET 40h........................ 50 SECONDARY DATA BUFFERING CONTROL REGISTER - OFFSET 40h.................. 51 Page 6 of 77 June 10, 2005 Revision 1.06
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION 8.1.36 8.1.37 8.1.38 8.1.39 8.1.40 8.1.41 8.1.42 8.1.43 8.1.44 8.1.45 8.1.46 8.1.47 8.1.48 8.1.49 8.1.50 8.1.51 8.1.52 8.1.53 8.1.54 8.1.55 8.1.56 8.1.57 8.1.58 8.1.59 8.1.60 8.1.61 8.1.62 8.1.63 8.1.64 9 9.1 9.2 9.3 9.4 9.5 10 10.1 10.2 10.3 10.4 11 12 MISCELLANEOUS CONTROL REGISTER - OFFSET 44h........................................... 52 EXTENDED CHIP CONTROL REGISTER 1 - OFFSET 48h......................................... 52 EXTENDED CHIP CONTROL REGISTER 2 - OFFSET 48h......................................... 53 ARBITER MODE REGISTER - OFFSET 50h................................................................. 53 ARBITER ENABLE REGISTER - OFFSET 54h.............................................................. 54 ARBITER PRIORITY REGISTER - OFFSET 58h ........................................................... 54 SERR# DISABLE REGISTER - OFFSET 5Ch ................................................................ 55 PRIMARY RETRY COUNTER REGISTER - OFFSET 60h............................................. 56 SECONDARY RETRY COUNTER REGISTER - OFFSET 64h....................................... 56 DISCARD TIMER CONTROL REGISTER - OFFSET 68h............................................. 57 RETRY AND TIMER STATUS REGISTER - OFFSET 6Ch ............................................ 57 OPAQUE MEMORY ENABLE REGISTER - OFFSET 70h ............................................ 57 OPAQUE MEMORY BASE REGISTER - OFFSET 74h ................................................. 58 OPAQUE MEMORY LIMIT REGISTER - OFFSET 74h ................................................ 58 OPAQUE MEMORY BASE UPPER 32-BIT REGISTER - OFFSET 78h ....................... 58 OPAQUE MEMORY LIMIT UPPER 32-BIT REGISTER - OFFSET 7Ch...................... 58 PCI-X CAPABILITY ID REGISTER - OFFSET 80h ....................................................... 58 NEXT CAPABILITY POINTER REGISTER - OFFSET 80h ........................................... 59 PCI-X SECONDARY STATUS REGISTER - OFFSET 80h............................................. 59 PCI-X BRIDGE PRIMARY STATUS REGISTER - OFFSET 84h ................................... 59 SECONDARY BUS UPSTREAM SPLIT TRANSACTION REGISTER - OFFSET 88h ... 61 PRIMARY BUS DOWNSTREAM SPLIT TRANSACTION REGISTER - OFFSET 8Ch .. 61 POWER MANAGEMENT ID REGISTER - OFFSET 90h............................................... 61 NEXT CAPABILITIES POINTER REGISTER - OFFSET 90h........................................ 62 POWER MANAGEMENT CAPABILITIES REGISTER - OFFSET 90h.......................... 62 POWER MANAGEMENT CONTROL AND STATUS REGISTER - OFFSET 94h ......... 62 PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER - OFFSET 94h ................. 63 SECONDARY BUS PRIVATE DEVICE MASK REGISTER - OFFSET B0h................... 63 MISCELLANEOUS CONTROL REGISTER 2 - OFFSET B8h ....................................... 64
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER .................................................................. 65 INSTRUCTION REGISTER..................................................................................................... 65 BYPASS REGISTER ................................................................................................................ 65 DEVICE ID REGISTER ........................................................................................................... 65 BOUNDARY SCAN REGISTER ............................................................................................. 66 JTAG BOUNDARY REGISTER ORDER................................................................................ 66 MAXIMUM RATINGS ............................................................................................................ 74 DC SPECIFICATIONS............................................................................................................. 74 AC SPECIFICATIONS............................................................................................................. 74 POWER CONSUMPTION ....................................................................................................... 75
ELECTRICAL INFORMATION.................................................................................................... 74
MECHANICAL INFORMATION.................................................................................................. 76 ORDERING INFORMATION........................................................................................................ 76
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
LIST OF TABLES
TABLE 3-1 PIN LIST 304-PIN PBGA........................................................................................................... 19 TABLE 4-1 PCI AND PCI-X TRANSACTIONS .......................................................................................... 22 TABLE 4-2 WRITE TRANSACTION FORWARDING ............................................................................... 23 TABLE 4-3 READ TRANSACTIN HANDLING.......................................................................................... 25 TABLE 4-4 DEVICE NUMBER TO IDSEL.................................................................................................. 31 TABLE 5-1 SUMMARY OF TRANSACTION ORDERING IN PCI MODE ............................................... 33 TABLE 5-2 SUMMARY OF TRANSACTION ORDERING IN PCI-X MODE ........................................... 33 TABLE 6-1 PROGRAMMABLE PULL-UP CIRCUIT................................................................................. 35 TABLE 6-2 DRIVER IMPEDANCE SELECTION ....................................................................................... 36 TABLE 7-1 DELAY TIMES FOR DE-ASSERTION OF S_RST# ................................................................ 38 TABLE 7-2 DE-ASSERTION OF S_RST#.................................................................................................... 38 TABLE 8-1 CONFIGURATION SPACE MAP ............................................................................................. 41 TABLE 9-1 JTAG BOUNDARY SCAN REGISTER .................................................................................... 66 TABLE 10-1 AC TIMING SPECIFICATIONS PCI-X MODE...................................................................... 75 TABLE 10-2 AC TIMING SPECIFICATIONS CONVENTIONAL PCI MODE.......................................... 75
LIST OF FIGURES
FIGURE 10-1 PCI SIGNAL TIMING MEASUREMENTS ........................................................................... 74 FIGURE 11-1 PACKAGE DIAGRAM 31 X 31MM 304-PIN HPBGA ........................................................... 76
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
1
DESCRIPTION
The PI7C21P100 is a 2-port PCI-X 2.0 Bridge designed to be compliant with the PCI-X Addendum to the Local Bus Specification Revision 1.0a. The PI7C21P100 is able to handle 64-bit data at a maximum bus frequency of 133MHz. The PI7C21P100 is designed for high speed applications such as Ethernet, SCSI, and Fibre Channel. The PI7C21P100 may also be used for bus expansion, frequency isolations/translations, or PCI-X to PCI isolations/translations.
2
FEATURES
INDUSTRY STANDARDS COMPLIANCE PCI-X Addendum to the Local Bus Specification Revision 1.0a (Mode 1 only) PCI Local Bus Specification Revision 2.2 PCI-to-PCI Bridge Architecture Specification Revision 1.1 PCI Power Management Interface Specification Revision 1.1 * Supports D0 and D3 power states INTERFACE 3.3V signaling with 5V tolerance 133MHz / 64-bit operation on both buses Dual address cycle support Concurrent primary and secondary bus operation Primary and secondary may be run in either PCI mode or PCI-X Mode 1 Asynchronous operation support Programmable internal arbiter with support for up to 6 external masters on the secondary bus * Internal arbiter may be disabled to use an external arbiter IEEE 1149.1 JTAG support OPERATION Type 0 and Type 1 configuration support Configuration register access from both primary and secondary buses 2KB of buffering for upstream memory burst read commands 2KB of buffering for downstream memory burst read commands 1KB of buffering for upstream posted memory write commands 1KB of buffering for downstream posted memory write commands Support for up to 8 active transactions in each direction ADDITIONAL FEATURES Capabilities pointer Ability to define an opaque memory address Definable base address register Secondary side PCI-X device privatization PACKAGING 304-pin PBGA, 31 x 31 mm
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
3
3.1
SIGNAL DEFINITIONS
SIGNAL TYPES
Signal Type I O P TS STS OD IU ID Description Input Only Output Only Power Tri-State bi-directional Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when deasserting. Open Drain Internal pull-up on signal Internal pull-down on signal
3.2
SIGNALS
Signal names that end with "#" are active LOW.
3.2.1
PRIMARY BUS INTERFACE SIGNALS
Name P_AD[31:0] Pin # J23, M21, M22, L21, L22, G23, K20, E23, K21, D23, K22, J21, J22, H21, H22, G21, B20, G22, F20, F22, D18, C19, C17, B17, A20, C16, B16, A19, C15, B14, C13, B13 A15, D14, B18, A13 Type TS Description Primary Address / Data: Multiplexed address and data bus. Address is indicated by P_FRAME# assertion. Write data is stable and valid when P_IRDY# is asserted and read data is stable and valid when P_TRDY# is asserted. Data is transferred on rising clock edges when both P_IRDY# and P_TRDY# are asserted. During bus idle, PI7C21P100 drives P_AD[31:0] to a valid logic level when P_GNT# is asserted. Primary Command/Byte Enables: Multiplexed command field and byte enable field. During address phase, the initiator drives the transaction type on these pins. After that, the initiator drives the byte enables during data phases. During bus idle, PI7C21P100 drives P_CBE[3:0]# to a valid logic level when P_GNT# is asserted. Primary Parity. P_PAR is even parity of P_AD[31:0] and P_CBE[3:0] (i.e. an even number of 1's). P_PAR is valid and stable one cycle after the address phase (indicated by assertion of P_FRAME#) for address parity. For write data phases, P_PAR is valid one clock after P_IRDY# is asserted. For read data phase, P_PAR is valid one clock after P_TRDY# is asserted. Signal P_PAR is tri-stated one cycle after the P_AD lines are tri-stated. During bus idle, PI7C21P100 drives P_PAR to a valid logic level when P_GNT# is asserted. Primary FRAME (Active LOW). Driven by the initiator of a transaction to indicate the beginning and duration of an access. The de-assertion of P_FRAME# indicates the final data phase requested by the initiator. Before being tri-stated, it is driven HIGH for one cycle. Primary IRDY (Active LOW). Driven by the initiator of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven HIGH for one cycle.
P_CBE[3:0]#
TS
P_PAR
C18
TS
P_FRAME#
A17
STS
P_IRDY#
A16
STS
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
Name P_TRDY# Pin # B15 Type STS Description Primary TRDY (Active LOW). Driven by the target of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven HIGH for one cycle. Primary Device Select (Active LOW). Asserted by the target indicating that the device is accepting the transaction. As a master, PI7C21P100 waits for the assertion of this signal within 5 cycles of P_FRAME# assertion; otherwise, terminate with master abort. Before tri-stated, it is driven HIGH for one cycle. Primary STOP (Active LOW). Asserted by the target indicating that the target is requesting the initiator to stop the current transaction. Before tri-stated, it is driven HIGH for one cycle. Primary LOCK (Active LOW). Asserted by an initiator, one clock cycle after the first address phase of a transaction, attempting to perform an operation that may take more than one PCI transaction to complete. Primary ID Select. Used as a chip select line for Type 0 configuration access to PI721P100 configuration space. Primary Parity Error (Active LOW). Asserted when a data parity error is detected for data received on the primary interface. Before being tri-stated, it is driven HIGH for one cycle. Primary System Error (Active LOW). Can be driven LOW by any device to indicate a system error condition. PI7C21P100 drives this pin on: Address parity error Posted write data parity error on target bus Secondary S_SERR# asserted Master abort during posted write transaction Target abort during posted write transaction Posted write transaction discarded Delayed write request discarded Delayed read request discarded Delayed transaction master timeout This signal requires an external pull-up resistor for proper operation. Primary Request (Active LOW): This is asserted by PI7C21P100 to indicate that it wants to start a transaction on the primary bus. PI7C21P100 de-asserts this pin for at least 2 PCI clock cycles before asserting it again. Primary Grant (Active LOW): When asserted, PI7C21P100 can access the primary bus. During idle and P_GNT# asserted, PI7C21P100 will drive P_AD, P_CBE, and P_PAR to valid logic levels. Primary RESET (Active LOW): When P_RESET# is active, all PCI signals should be asynchronously tristated.
P_DEVSEL#
D21
STS
P_STOP#
C4
STS
P_LOCK#
C14
I
P_IDSEL P_PERR#
B19 C8
I STS
P_SERR#
B4
OD
P_REQ#
B21
TS
P_GNT#
C20
I
P_RST#
E22
I
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
3.2.2
PRIMARY BUS INTERFACE SIGNALS - 64-BIT EXTENSION
Name P_AD[63:32] Pin # B11, D10, C10, A4, B10, C9, B9, A3, B8, B3, C7, B7, D6, B6, B5, C2, D2, F4, E3, F3, B1, F2, G3, H3, H2, E1, J3, G1, H1, J2, J1, L1 Type TS Description Primary Upper 32-bit Address / Data: Multiplexed address and data bus providing an additional 32 bits to the primary. When a dual address command is used and P_REQ64# is asserted, the initiator drives the upper 32 bits of the 64-bit address. Otherwise, these bits are undefined and driven to valid logic levels. During the data phase of a transaction, the initiator drives the upper 32 bits of the 64-bit write data, or the target drives the upper 32 bits of the 64-bit read data, when P_REQ64# and P_ACK64# are both asserted. Otherwise, these bits are pulled up to a valid logic level through external resistors. Primary Upper 32-bit Command/Byte Enables: Multiplexed command field and byte enable field. During address phase, when the dual address command is used and P_REQ64# is asserted, the initiator drives the transaction type on these pins. Otherwise, these bits are undefined, and the initiator drives a valid logic level onto the pins. For read and write transactions, the initiator drives these bits for the P_AD[63:32] data bits when P_REQ64# and P_ACK64# are both asserted. When not driven, these bits are pulled up to a valid logic level through external resistors. Primary Upper 32-bit Parity: P_PAR64 carries the even parity of P_AD[63:32] and P_CBE[7:4] for both address and data phases. P_PAR64 is driven by the initiator and is valid 1 cycle after the first address phase when a dual address command is used and P_REQ64# is asserted. P_PAR64 is valid 1 clock cycle after the second address phase of a dual address transaction when P_REQ64# is asserted. P_PAR64 is valid 1 cycle after valid data is driven when both P_REQ64# and P_ACK64# are asserted for that data phase. P_PAR64 is driven by the device driving read or write data 1 cycle after the P_AD lines are driven. P_PAR64 is tri-stated 1 cycle after the P_AD lines are tri-stated. Devices receive data sample P_PAR64 as an input to check for possible parity errors during 64-bit transactions. When not driven, P_PAR64 is pulled up to a valid logic level through external resistors. Primary 64-bit Transfer Request: P_REQ64# is asserted by the initiator to indicate that the initiator is requesting a 64-bit data transfer. P_REQ64# has the same timing as P_FRAME#. When P_REQ64# is asserted LOW during reset, a 64-bit data path is supported. When P_REQ64# is HIGH during reset, PI7C21P100 drives P_AD[63:32], P_CBE[7:4], and P_PAR64 to valid logic levels. When deasserting, P_REQ64# is driven HIGH for 1 cycle and then sustained by an external pull-up resistor. Primary 64-bit Transfer Acknowledge: P_ACK64# is asserted by the target only when P_REQ64# is asserted by the initiator to indicate the target's ability to transfer data using 64 bits. P_ACK64# has the same timing as P_DEVSEL#. When deasserting, P_ACK64# is driven HIGH for 1 cycle and then is sustained by an external pull-up resistor.
P_CBE[7:4]#
A7, B12, C11, A5
TS
P_PAR64
A9
TS
P_REQ64#
C12
STS
P_ACK64#
A2
STS
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
3.2.3
SECONDARY BUS INTERFACE SIGNALS
Name S_AD[31:0] Pin # N22, N21, P22, P21, M23, P20, N23, R22, T23, R21, W23, T22, U22, U21, V22, V21, W21, V20, AA20, AB18, Y18, AA16, AB15, AC17, AA13, AA12, AC15, AB11, AC11, AC9, AB9, AA9 AA15, AB14, AB16, AB12 Type TS Description Secondary Address/Data: Multiplexed address and data bus. Address is indicated by S_FRAME# assertion. Write data is stable and valid when S_IRDY# is asserted and read data is stable and valid when S_IRDY# is asserted. Data is transferred on rising clock edges when both S_IRDY# and S_TRDY# are asserted. During bus idle, PI7C21P100 drives S_AD[31:0] to a valid logic level when the bridge is granted the bus. Secondary Command/Byte Enables: Multiplexed command field and byte enable field. During address phase, the initiator drives the transaction type on these pins. The initiator then drives the byte enables during data phases. During bus idle, PI7C21P100 drives S_CBE[3:0] to a valid logic level when the bridge is granted the bus. Secondary Parity: S_PAR is an even parity of S_AD[31:0] and S_CBE[3:0] (i.e. an even number of 1's). S_PAR is valid and stable one cycle after the address phase (indicated by assertion of S_FRAME#) for address parity. For write data phases, S_PAR is valid one clock after S_IRDY# is asserted. For read data phase, S_PAR is valid one clock after S_TRDY# is asserted. Signal S_PAR is tri-stated one cycle after the S_AD lines are tri-stated. During bus idle, PI7C21P100 drives S_PAR to a valid logic level when the bridge is granted the bus. Secondary FRAME (Active LOW): Driven by the initiator of a transaction to indicate the beginning and duration of an access. The de-assertion of S_FRAME# indicates the final data phase requested by the initiator. Before being tri-stated, it is driven HIGH for one cycle. Secondary IRDY (Active LOW): Driven by the initiator of a transaction to indicate its ability to complete current data phase on the secondary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven HIGH for one cycle. Secondary TRDY (Active LOW): Driven by the target of a transaction to indicate its ability to complete current data phase on the secondary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven HIGH for one cycle. Secondary Device Select (Active LOW): Asserted by the target indicating that the device is accepting the transaction. As a master, PI7C21P100 waits for the assertion of this signal within 5 cycles of S_FRAME# assertion; otherwise, terminate with master abort. Before tri-stated, it is driven HIGH for one cycle. Secondary STOP (Active LOW): Asserted by the target indicating that the target is requesting the initiator to stop the current transaction. Before tri-stated, it is driven HIGH for one cycle. Secondary LOCK (Active LOW): Asserted by an initiator, one clock cycle after the first address phase of a transaction, when it is propagating a locked transaction downstream. PI7C21P100 does not propagate locked transactions upstream. Secondary Parity Error (Active LOW): Asserted when a data parity error is detected for data received on the secondary interface. Before being tri-stated, it is driven HIGH for one cycle.
S_CBE[3:0]#
TS
S_PAR
AA17
TS
S_FRAME#
AA14
STS
S_IRDY#
AC19
STS
S_TRDY#
Y14
STS
S_DEVSEL#
AC21
STS
S_STOP#
AB20
STS
S_LOCK#
AC20
STS
S_PERR#
AB17
STS
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
Name S_SERR# S_REQ[6:2]# Pin # AB19 AC3, AB5, AB3, W2, AA2 AA23 Type I I Description Secondary System Error (Active LOW): Can be driven LOW by any device to indicate a system error condition. Secondary Request (Active LOW): This is asserted by an external device to indicate that it wants to start a transaction on the secondary bus. The input is externally pulled up through a resistor to VDD. Secondary Request (Active LOW): When the internal arbiter is enabled, this is asserted by an external device to indicate that it wants to start a transaction on the secondary bus. The input is externally pulled up through a resistor to VDD. When the internal arbiter is disabled, this is used by PI7C21P100 as its GNT input. Secondary Grant (Active LOW): PI7C21P100 asserts these pins to allow external masters to access the secondary bus. PI7C21P100 de-asserts these pins for at least 2 PCI clock cycles before asserting it again. During idle and S_GNT# deasserted, PI7C21P100 will drive S_AD, S_CBE, and S_PAR. Secondary Grant (Active LOW): When the internal arbiter is enabled, PI7C21P100 asserts this pin to allow external masters to access the secondary bus. PI7C21P100 de-asserts this pin for at least 2 PCI clock cycles before asserting it again. During idle and S_GNT# deasserted, PI7C21P100 will drive S_AD, S_CBE, and S_PAR. When the internal arbiter is disabled, this is used by PI7C21P100 as its REQ output. Secondary RESET (Active LOW): Asserted when any of the following conditions are met: 1. Signal P_RESET# is asserted. 2. Secondary reset bit in bridge control register in configuration space is set. 3. The chip reset bit in the chip control register in configuration space is set. When asserted, all control signals are tri-stated and zeroes are driven on S_AD, S_CBE, S_PAR, and S_PAR64.
S_REQ[1]#
I
S_GNT[6:2]#
AC4, AB4, AC5, Y2, AB1
TS
S_GNT[1]#
AA19
TS
S_RST#
U23
O
3.2.4
SECONDARY BUS INTERFACE SIGNALS - 64-BIT EXTENSION
Name S_AD[63:32] Pin # AB8, AB7, AA7, AB6, AA6, AA5, Y6, Y3, V2, V4, U2, U3, T2, T3, R2, R3, P2, Y1, P3, W1, P4, U1, N2, N3, M2, M3, R1, L2, L3, K2, K3, K4 Y10, AB10, AA11, AC8 Type TS Description Secondary Upper 32-bit Address/Data: Multiplexed address and data bus. Address is indicated by S_FRAME# assertion. Write data is stable and valid when S_IRDY# is asserted and read data is stable and valid when S_IRDY# is asserted. Data is transferred on rising clock edges when both S_IRDY# and S_TRDY# are asserted. During bus idle, PI7C21P100 drives S_AD to a valid logic level when the bridge is granted the bus. Secondary Upper 32-bit Command/Byte Enables: Multiplexed command field and byte enable field. During address phase, the initiator drives the transaction type on these pins. The initiator then drives the byte enables during data phases. During bus idle, PI7C21P100 drives S_CBE[7:0] to a valid logic level when the bridge is granted the bus.
S_CBE[7:4]#
TS
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
Name S_PAR64 Pin # AA10 Type TS Description Secondary Upper 32-bit Parity: S_PAR64 carries the even parity of S_AD[63:32] and S_CBE[7:4] for both address and data phases. S_PAR64 is driven by the initiator and is valid 1 cycle after the first address phase when a dual address command is used and S_REQ64# is asserted. S_PAR64 is valid 1 clock cycle after the second address phase of a dual address transaction when S_REQ64# is asserted. S_PAR64 is valid 1 cycle after valid data is driven when both S_REQ64# and S_ACK64# are asserted for that data phase. S_PAR64 is driven by the device driving read or write data 1 cycle after the S_AD lines are driven. S_PAR64 is tri-stated 1 cycle after the S_AD lines are tri-stated. Devices receive data sample S_PAR64 as an input to check for possible parity errors during 64-bit transactions. When not driven, S_PAR64 is pulled up to a valid logic level through external resistors. Secondary 64-bit Transfer Request: S_REQ64# is asserted by the initiator to indicate that the initiator is requesting a 64-bit data transfer. S_REQ64# has the same timing as S_FRAME#. When S_REQ64# is asserted LOW during reset, a 64-bit data path is supported. When S_REQ64# is HIGH during reset, PI7C21P100 drives S_AD[63:32], S_CBE[7:4], and S_PAR64 to valid logic levels. When deasserting, S_REQ64# is driven to a deasserted state for 1 cycle and then sustained by an external pull-up resistor. Secondary 64-bit Transfer Acknowledge: S_ACK64# is asserted by the target only when S_REQ64# is asserted by the initiator to indicate the target's ability to transfer data using 64 bits. S_ACK64# has the same timing as S_DEVSEL#. When deasserting, S_ACK64# is driven to a deasserted state for 1 cycle and then is sustained by an external pull-up resistor.
S_REQ64#
AB13
STS
S_ACK64#
AA8
STS
3.2.5
CLOCK SIGNALS
Name P_CLK Pin # E21 Type I Description Primary Clock Input: Provides timing for all transactions on the primary interface. For conventional PCI mode, the input clock frequency may be between 0 - 66MHz. In PCI-X mode, the input clock frequency may be between 66 - 133MHz. See Section 6 for limitations. Secondary Clock Input: Provides timing for all transactions on the secondary interface. For conventional PCI mode, the input clock frequency may be between 0 - 66MHz. In PCI-X mode, the input clock frequency may be between 66 - 133MHz. See Section 6 for limitations. If the primary bus is running at 133MHz, the minimum frequency that may be supplied to S_CLK is 33MHz.
S_CLK
AB23
I
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
3.2.6
STRAPPING PINS AND MISCELLANEOUS SIGNALS
Name S__ARB# Pin # T21 Type I Description Internal Arbiter Enable: This pin is used by PI7C21P100 to determine whether the secondary bus uses the internal arbiter or external arbiter. 0: Enable the internal arbiter S_SEL100 V3 I 1: Disable the internal arbiter and use an external arbiter Secondary Bus Maximum Frequency: This pin is used to determine the maximum frequency on the secondary bus when in PCI-X mode. In PCI mode, the pin has no function and should not be left floating. 0: Set secondary interface to 133MHz S_PCIXCAP R23 I 1: Set secondary interface to 100MHz Secondary Bus PCI-X Capable: This pin is used with S_SEL100 to determine the frequency and mode for the secondary bus. There are three conditions for this pin determining the capability of the secondary bus: Ground: Not capable of PCI-X mode Pull-down: PCI-X 66MHz S_PCIXCAP_PU AA1 I Not connected: PCI-X 133MHz S_PCIXCAP Pull-up Driver: This pin is used with S_PCIXAP as part of a programmable pull-up circuit to determine the state of S_PCIXCAP. A 1kohm resistor must be placed between this pin and S_PCIXCAP. Secondary Driver Mode: This pin controls the output impedance of the secondary drivers to account for the number of loads on the secondary bus. 0: default impedance 1: select alternate impedance P_DRVR E2 ID See Table 6-2 for impedance values. Primary Driver Mode Control: Controls the output impedance of the primary bus drivers to account for the number of loads on the primary bus. 0: Default impedance S_CLK_STABLE W3 I 1: Select alternate impedance S_CLK Input Stable: Determines when the S_CLK is stable to resolve when S_RST# can by de-asserted. 0: S_CLK is not stable S_IDSEL AA22 I 1: S_CLK is stable Initialization Device Select: S_IDSEL is used as a chip select during configuration reads and writes on the secondary bus. Applications that do not require access to PI7C21P100's configuration registers from the secondary side should pull this pin LOW.
S_DRVR
AC7
ID
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
64BIT_DEV# Y22 I PCI-X Device Bus Width: 64BIT_DEV# sets bit 16 of the PCI-X Bridge Status Register to support system management software. This signal does not change the behavior of the bridge. 0: Sets bit 16 of the PCI-X bridge status register to 1 BAR_EN G2 I 1: Sets bit 16 of the PCI-X bridge status register to 0 Base Address Register Enable: BAR_EN is used to enable the base address at reset or power up. When enabled, the 64-bit register at offset 10h and offset 14h is used to claim a 1MB memory region. 0: Disabled - register returns 0 and no memory region is claimed 1: Enabled - bits 63:20 can be written by software to claim a 1MB memory region IDSEL Reroute Enable: Controls the IDSEL reroute function at reset or power up. The reset value of the secondary bus private device mask register is changed according to the value of this pin. 0: Reset value of the secondary bus private device mask register is 00000000h 1: Reset value of the secondary bus private device mask register is 22F20000h Opaque Region Enable: Used to enable the opaque memory region at reset or power up. Controls bit[0] offset 70h. 0: Disable opaque memory address range P_CFG_BUSY C6 I 1: Enable opaque memory address range Primary Configuration Busy: Determines the value of bit [2] offset 44h to sequence initialization on the primary and secondary buses for applications that require bridge configuration from the secondary bus. Applications that do not require configuration from the secondary bus should pull this pin down to ground. 0: Type 0 configuration commands accepted normally on the primary bus. 1: Type 0 configuration commands are retried on the primary bus. Reserved. Must be tied to ground.
IDSEL_ROUTE
AC22
I
OPAQUE_EN
AA18
I
RESERVED
D1
-
3.2.7
JTAG BOUNDARY SCAN AND TEST SIGNALS
Name TCK TMS TDO TDI TRST# Pin # F21 D22 B23 C22 C23 Type IU IU O IU IU Description Test Clock. Used to clock state information and data into and out of the PI721P100 during boundary scan. Test Mode Select. Used to control the state of the Test Access Port controller. Test Data Output. Used as the serial output for the test instructions and data from the test logic. Test Data Input. Serial input for the JTAG instructions and test data. Test Reset. Active LOW signal to reset the Test Access Port (TAP) controller into an initialized state.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
3.2.8
TEST SIGNALS
Name T_DI1 Pin # Y21 Type IU Description PLL Bypass Control for PCI-X Mode. The strapped value of this pin (at P_RST# deassertion) controls whether the internal PLL's are bypassed in PCI-X mode. HIGH: PLL's are used in PCI-X mode T_DI2 AA4 IU LOW: PLL's are bypassed in PCI-X mode Shorten Initialization Period. Controls the period for the following signals during initialization. LOW: Shorten periods TPIRSTDLY - 5 Primary Clocks TXCAP - 6 Primary Clocks TSIRSTDLY - 40 Secondary Clocks TSRSTDLY - 11 Secondary Clocks + 7 Primary Clocks HIGH: Normal initialization TPIRSTDLY - See Table 7-2 TXCAP - See Table 7-2 TSIRSTDLY - See Table 7-2 TSRSTDLY - See Table 7-2 PLL Test Control. Controls along with the internal PLL testing. T_RI H H L T_MODECTL L H H XCLK_OUT Z P_CLK* S_CLK**
T_MODECTL T_RI XCLK_OUT
C1 W22 D3
I I I
T_RI
W22
I
* P_PLL enabled, S_PLL disabled **P_PLL disabled, S_PLL enabled PLL Bypass Control for PCI Mode. The strapped value of this pin (at T_RI) controls whether the internal PLL's are bypassed in PCI mode. 1: PLL's are bypassed in PCI mode
TEST_CE0
Y23
ID
0 and T_MODECTL=0: PLL's are used in PCI mode Reserved. Chip testing only. Tie LOW for normal operation.
3.2.9
POWER AND GROUND SIGNALS
Name P_VDDA P_VSSA S_VDDA S_VSSA VDD Pin # A21 D16 AB21 Y16 D9, D11, D13, D15, J4, J20, L4, L20, N4, N20, R4, R20, Y9, Y11, Y13, Y15 Type P P P P P Description 2.5V Power: Power supply to the PLL for the primary clock domain. 2.5V Power: Ground for the PLL for the primary clock domain. 2.5V Power: Power supply to the PLL for the secondary clock domain. 2.5V Power: Ground for the PLL for the secondary clock domain. 2.5 Power: Power supply for the internal logic
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
Name VDD2 Pin # A8, A12, A22, C5, D5, D7, D17, D19, E4, E20, G4, G20, H23, M1, T1, U4, U20, W4, W20, Y5, Y7, Y17, Y19, AC2, AC12, AC16 A1, A6, A10, A11, A14, A18, A23, B2, B22, C3, C21, D4, D8, D12, D20, F1, F23, H4, H20, K1, K23, L23, M4, M20, N1, P1, P23, T4, T20, V1, V23, Y4, Y8, Y12, Y20, AA3, AA21, AB2, AB22, AC1, AC6, AC10, AC13, AC14, AC18, AC23 Type P Description 3.3 Power: Power supply for the I/O
VSS
P
Ground
3.3
PIN LIST
Table 3-1 PIN LIST 304-PIN PBGA
BALL LOCATION A1 A3 A5 A7 A9 A11 A13 A15 A17 A19 A21 A23 B2 B4 B6 B8 B10 B12 B14 B16 B18 B20 B22 C1 C3 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 PIN NAME VSS P_AD[56] P_CBE[4]# P_CBE[7]# P_PAR64 VSS P_CBE[0]# P_CBE[3]# P_FRAME# P_AD[4] P_VDDA VSS VSS P_SERR# P_AD[50] P_AD[55] P_AD[59] P_CBE[6]# P_AD[2] P_AD[5] P_CBE[1]# P_AD[15] VSS T_MODECTL VSS VDD2 P_AD[53] P_AD[58] P_CBE[5]# P_AD[1] P_AD[3] P_AD[9] P_AD[10] VSS TRST# TYPE P TS TS TS TS P TS TS STS TS P P P OD TS TS TS TS TS TS TS TS P I P P TS TS TS TS TS TS TS P I BALL LOCATION A2 A4 A6 A8 A10 A12 A14 A16 A18 A20 A22 B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 C2 C4 C6 C8 C10 C12 C14 C16 C18 C20 C22 D1 PIN NAME P_ACK64# P_AD[60] VSS VDD2 VSS VDD2 VSS P_IRDY# VSS P_AD[7] VDD2 P_AD[43] P_AD[54] P_AD[49] P_AD[52] P_AD[57] P_AD[63] P_AD[0] P_TRDY# P_AD[8] P_IDSEL P_REQ# TDO P_AD[48] P_STOP# P_CFG_BUSY P_PERR# P_AD[61] P_REQ64# P_LOCK# P_AD[6] P_PAR P_GNT# TDI RESERVED TYPE STS TS P P P P P STS P TS P TS TS TS TS TS TS TS STS TS I TS O TS STS I STS TS STS I TS TS I I -
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
BALL LOCATION D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 E1 E3 E20 E22 F1 F3 F20 F22 G1 G3 G20 G22 H1 H3 H20 H22 J1 J3 J20 J22 K1 K3 K20 K22 L1 L3 L20 L22 M1 M3 M20 M22 N1 N3 N20 N22 P1 P3 P20 P22 R1 R3 R20 R22 T1 T3 T20 T22 U1 U3 U20 U22 PIN NAME P_AD[47] VSS P_AD[51] VSS P_AD[62] VSS P_CBE[2]# P_VSSA P_AD[11] VSS TMS P_AD[38] P_AD[45] VDD2 P_RST# VSS P_AD[44] P_AD[13] P_AD[12] P_AD[36] P_AD[41] VDD2 P_AD[14] P_AD[35] P_AD[40] VSS P_AD[17] P_AD[33] P_AD[37] VDD P_AD[19] VSS S_AD[33] P_AD[25] P_AD[21] P_AD[32] S_AD[35] VDD P_AD[27] VDD2 S_AD[38] VSS P_AD[29] VSS S_AD[40] VDD S_AD[31] VSS S_AD[45] S_AD[26] S_AD[29] S_AD[37] S_AD[48] VDD S_AD[24] VDD2 S_AD[50] VSS S_AD[20] S_AD[42] S_AD[52] VDD2 S_AD[19] TYPE TS P TS P TS P TS P TS P I TS TS P I P TS TS TS TS TS P TS TS TS P TS TS TS P TS P TS TS TS TS TS P TS P TS P TS P TS P TS P TS TS TS TS TS P TS P TS P TS TS TS P TS BALL LOCATION D3 D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 E2 E4 E21 E23 F2 F4 F21 F23 G2 G4 G21 G23 H2 H4 H21 H23 J2 J4 J21 J23 K2 K4 K21 K223 L2 L4 L21 L23 M2 M4 M21 M23 N2 N4 N21 N23 P2 P4 P21 P23 R2 R4 R21 R23 T2 T4 T21 T23 U2 U4 U21 U23 PIN NAME XCLK_OUT VDD2 VDD2 VDD VDD VDD VDD VDD2 VDD2 P_DEVSEL# P_AD[22] P_DRVER VDD2 P_CLK P_AD[24] P_AD[42] P_AD[46] TCK VSS BAR_EN VDD2 P_AD[16] P_AD[26] P_AD[39] VSS P_AD[18] VDD2 P_AD[34] VDD P_AD[20] P_AD[31] S_AD[34] S_AD[32] P_AD[23] VSS S_AD[36] VDD P_AD[28] VSS S_AD[39] VSS P_AD[30] S_AD[27] S_AD[41] VDD S_AD[30] S_AD[25] S_AD[47] S_AD[43] S_AD[28] VSS S_AD[49] VDD S_AD[22] S_PCIXCAP S_AD[51] VSS S_ARB# S_AD[23] S_AD[53] VDD2 S_AD[18] S_RST# TYPE I P P P P P P P P STS TS I P I TS TS TS I P I P TS TS TS P TS P TS P TS TS TS TS TS P TS P TS P TS P TS TS TS P TS TS TS TS TS P TS P TS I TS P I TS TS P TS O
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
BALL LOCATION V1 V3 V20 V22 W1 W3 W20 W22 Y1 Y3 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 Y21 Y23 AA2 AA4 AA6 AA8 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AB1 AB3 AB5 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AC2 AC4 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 PIN NAME VSS S_SEL100 S_AD[14] S_AD[17] S_AD[44] S_CLK_STABLE VDD2 T_RI S_AD[46] S_AD[56] VDD2 VDD2 VDD VDD VDD VDD VDD2 VDD2 T_DI1 TEST_CE0 S_REQ[2]# T_DI2 S_AD[59] S_ACK64# S_PAR64 S_AD[6] S_FRAME# S_AD[10] OPAQUE_EN S_AD[13] S_IDSEL S_GNT[2]# S_REQ[4]# S_REQ[5]# S_AD[62] S_AD[1] S_AD[4] S_REQ64# S_AD[9] S_PERR# S_SERR# S_VDDA S_CLK VDD2 S_GNT[6]# VSS S_CBE[4]# VSS VDD2 VSS VDD2 VSS S_LOCK# IDSEL_ROUTE TYPE P I TS TS TS I P I TS TS P P P P P P P P I I I I TS STS TS TS STS TS I TS I TS I I TS TS TS STS TS STS I P I P TS P TS P P P P P STS I BALL LOCATION V2 V4 V21 V23 W2 W4 W21 W23 Y2 Y4 Y6 Y8 Y10 Y12 Y14 Y16 Y18 Y20 Y22 AA1 AA3 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AB2 AB4 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC1 AC3 AC5 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC23 PIN NAME S_AD[55] S_AD[54] S_AD[16] VSS S_REQ[3]# VDD2 S_AD[15] S_AD[21] S_GNT[3]# VSS S_AD[57] VSS S_CBE[7]# VSS S_TRDY# S_VSSA S_AD[11] VSS 64BIT_DEV# S_PCIXCAP_PU VSS S_AD[58] S_AD[61] S_AD[0] S_CBE[5]# S_AD[7] S_CBE[3]# S_PAR S_GNT[1]# VSS S_REQ[1]# VSS S_GNT[5]# S_AD[60] S_AD[63] S_CBE[6]# S_CBE[0]# S_CBE[2]# S_CBE[1]# S_AD[12] S_STOP# VSS VSS S_REQ[6]# S_GNT[4]# S_DRVR S_AD[2] S_AD[3] VSS S_AD[5] S_AD[8] S_IRDY# S_DEVSEL# VSS TYPE TS TS TS P I P TS TS TS P TS P TS P STS P TS P I I P TS TS TS TS TS TS TS TS P I P TS TS TS TS TS TS TS TS STS P P I TS I TS TS P TS TS STS STS P
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
4
PCI BUS OPERATION
This Chapter offers information about PCI transactions, transaction forwarding across PI7C21P100, and transaction termination. The PI7C21P100 has two 2KB buffers for read data buffering of upstream and downstream transactions. Also, PI7C21P100 has two 1KB buffers for write data buffering of upstream and downstream transactions.
4.1
TYPES OF TRANSACTIONS
This section provides a summary of PCI and PCI-X transactions performed by PI7C21P100. Table 4-1 lists the command code and name of each PCI and PCI-X transaction. The Master and Target columns indicate support for each transaction when PI7C21P100 initiates transactions as a master, on the primary and secondary buses, and when PI7C21P100 responds to transactions as a target, on the primary and secondary buses. Table 4-1 PCI AND PCI-X TRANSACTIONS
Types of Transactions 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate Initiates as Master Primary N Y Y Y N N Y Y N N N Y (Type 1 only) Y Y Y Y Secondary N Y Y Y N N Y Y N N Y Y Y Y Y Y Responds as Target Primary Secondary N N N N Y Y Y Y N N N N Y Y Y Y N N N N Y Y (Type 0 only) Y Y Y Y Y Y Y Y Y Y
As indicated in Table 4-1, the following commands are not supported by PI7C21P100: PI7C21P100 never initiates a transaction with a reserved command code and, as a target, PI7C21P100 ignores reserved command codes. PI7C21P100 does not generate interrupt acknowledge transactions. PI7C21P100 ignores interrupt acknowledge transactions as a target. PI7C21P100 does not respond to special cycle transactions. PI7C21P100 cannot guarantee delivery of a special cycle transaction to downstream buses because of the broadcast nature of the special cycle command and the inability to control the transaction as a target. To generate special cycle transactions on other buses, either upstream or downstream, Type 1 configuration write must be used.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
4.2
WRITE TRANSACTIONS
Write transactions are treated as posted write, delayed/split (PCI-X), or immediate write transactions. Table 4-2 shows the method of forwarding used for each type of write operation. Table 4-2 WRITE TRANSACTION FORWARDING
Type of Transaction Memory Write Memory Write and Invalidate Memory Write Block (PCI-X) I/O Write Type 0 Configuration Write Type 1 Configuration Write Type of Forwarding Posted Posted Posted Delayed / Split (PCI-X) Immediate on the primary bus. Delayed / Split (PCI-X) on the secondary bus. Delayed / Split (PCI-X)
4.2.1
MEMORY WRITE TRANSACTIONS
Posted write forwarding is used for "Memory Write", "Memory Write and Invalidate", and "Memory Write Block" transactions. When PI7C21P100 determines that a memory write transaction is to be forwarded across the bridge, PI7C21P100 asserts DEVSEL# with medium decode timing and TRDY# in the next cycle, provided that enough buffer space is available in the posted memory write queue for the address and at least one DWORD of data. Under this condition, PI7C21P100 accepts write data without obtaining access to the target bus. The PI7C21P100 can accept one DWORD of write data every PCI clock cycle. That is, no target wait state is inserted. The write data is stored in an internal posted write buffers and is subsequently delivered to the target. The PI7C21P100 continues to accept write data until one of the following events occurs: The initiator terminates the transaction by de-asserting FRAME# and IRDY#. An internal write address boundary is reached, such as a cache line boundary or an aligned 4KB boundary, depending on the transaction type. The posted write data buffer fills up. When one of the last two events occurs, the PI7C21P100 returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. Once the posted write data moves to the head of the posted data queue, PI7C21P100 asserts its request on the target bus. This can occur while PI7C21P100 is still receiving data on the initiator bus. When the grant for the target bus is received and the target bus is detected in the idle condition, PI7C21P100 asserts FRAME# and drives the stored write address out on the target bus. On the following cycle, PI7C21P100 drives the first DWORD of write data and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is received. As long as write data exists in the queue, PI7C21P100 can drive one DWORD of write data in each PCI clock cycle; that is, no master wait states are inserted. If write data is flowing through PI7C21P100 and the initiator stalls, PI7C21P100 will signal the last data phase for the current transaction at the target bus if the queue empties. PI7C21P100 will restart the follow-on transactions if the queue has new data.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION PI7C21P100 ends the transaction on the target bus when one of the following conditions is met: All posted write data has been delivered to the target. The target returns a target disconnect or target retry (PI7C21P100 starts another transaction to deliver the rest of the write data). The target returns a target abort (PI7C21P100 discards remaining write data). The master latency timer expires, and PI7C21P100 no longer has the target bus grant (PI7C21P100 starts another transaction to deliver remaining write data).
4.2.1.1
PCI-X TO PCI-X When both buses are operating in the PCI-X mode, PI7C21P100 passes the memory write command that it receives to the destination interface along with the originating byte count and transaction ID. PI7C21P100 attempts to transfer a memory write command when the transaction ends or a 128-byte boundary is crossed. As long as there is at least 128-byte of data in the data buffer or the end of transfer remains from the PCI-X memory write command when a 128-byte boundary is crossed, the transfer will continue. If a transaction is disconnected on the destination interface in the middle of a continuing transfer, the byte count and address are updated and the transaction is presented again on the destination interface. If a transaction is disconnected in the middle of a continuing transfer on the originating interface, the originator must present the transaction again with the updated byte count and address.
4.2.1.2
PCI TO PCI When both buses are operating in conventional PCI mode, the bridge passes the memory write command that it receives to the destination interface, unless PI7C21P100 is disconnected in the middle of a memory write and invalidate and is not on a cache line boundary. If this happens, the command will continue as a memory write when PI7C21P100 attempts to reconnect. PI7C21P100 attempts to transfer a memory write command when the transaction ends or a 128-byte boundary is crossed. As long as a 128-byte buffer is full or the end of transfer remains from the memory write command when a 128-byte boundary is crossed, the transfer will continue.
4.2.1.3
PCI TO PCI-X When the originating bus is operating in the conventional PCI mode and the destination bus is operating in the PCI-X mode, PI7C21P100 must buffer memory write transactions from the conventional PCI interface and count the number of bytes to be forwarded to the PCI-X interface. If the conventional PCI transaction uses the memory write command and some byte enables are not asserted, PI7C21P100 must use the PCI-X memory write command. If the conventional PCI command is memory write and all byte enables are asserted, PI7C21P100 will use the PCI-X memory write command. If the conventional transaction uses the memory write and invalidate command, PI7C21P100 uses the PCI-X memory write block command. PI7C21P100 attempts to transfer the write data on the PCI-X interface as soon as the transaction ends or a 128-byte boundary is crossed. Writes greater than 128 bytes are possible only if more than one 128-byte sector fills up before the write operation is issued on the PCIX interface. Page 24 of 77 June 10, 2005 Revision 1.06
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4.2.1.4
PCI-X TO PCI When the originating bus is operating in the PCI-X mode and the destination bus is operating in the conventional PCI mode, PI7C21P100 uses the PCI conventional memory write command for both the PCI-X memory write and PCI-X memory write block commands. PI7C21P100 attempts to transfer write data on the conventional PCI interface when the PCI-X data crosses a 128-byte boundary or the end of the PCI-X transfer occurs. As long as a 128byte buffer is full, or the end of transfer remains from the PCI-X memory write command when a 128-byte boundary is crossed, the transfer will continue on the conventional PCI interface.
4.2.2
DELAYED/SPLIT WRITE TRANSACTIONS
Delayed/Split write forwarding is used for I/O write transactions, Type 1 configuration write transactions, and Type 0 configuration write transactions. Delayed/Split write forwarding transactions are retried on the originating bus, completed on the destination bus (if necessary), and then completed on the originating bus. For DWORD transactions, PI7C21P100 uses delayed transactions in conventional PCI mode and split requests in PCI-X mode. Only one request queue entry is allowed for either delayed or split write transactions.
4.2.3
IMMEDIATE WRITE TRANSACTIONS
PI7C21P100 considers Type 0 configuration writes on the primary bus meant for the bridge as immediate write transactions for the bridge. PI7C21P100 will execute the transaction and indicate its completion by accepting the DWORD of data immediately.
4.3
READ TRANSACTIONS
Read transactions are treated as delayed read for conventional PCI mode, split read for PCI-X mode, or immediate read. Table 4-3 shows the read behavior. Table 4-3 READ TRANSACTIN HANDLING
Type of Transaction Memory Read Memory Read Line Memory Read Multiple Memory Read DWORD (PCI-X mode) Memory Read Block (PCI-X mode) I/O Read Type 0 Configuration Read Type 1 Configuration Read Type of Handling Delayed Delayed Delayed Split (PCI-X mode) Split (PCI-X mode) Delayed/Split (PCI-X) Immediate on the primary bus, Delayed/Split (PCI-X mode) on the secondary bus Delayed/Split (PCI-X mode)
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4.3.1
MEMORY READ TRANSACTIONS
Memory data is transferred from the originating side of PI7C21P100 to the destination side using PCI memory read, memory read line, memory read multiple, PCI-X memory read DWORD, and PCI-X memory read block transactions. All memory read transactions are either delayed or split on the originating side of PI7C21P100 depending on the mode of the originating side.
4.3.1.1
PCI-X TO PCI-X No translation is needed for these transactions. The amount of data that is fetched is controlled by the downstream and upstream split transaction control register. The split transaction capacity and split transaction commitment limit fields control how much data is requested at any one time.
4.3.1.2
PCI TO PCI No translation is needed for these transactions. Memory Read - Fetches only the requested DWORD if the command targets a nonprefetchable memory space. Bits [25:24] offset 40h and bits [9:8] offset 40h control the mode of prefetching for memory read transactions in the prefetchable range on the secondary and primary bus respectively. The default is up to one cache line will be prefetched. Memory Read Line - Bits [23:22] offset 40h and bits [7:6] offset 40h control the mode of prefetching for memory read line transactions in the prefetchable range on the secondary and primary bus respectively. The default is up to one cache line will be prefetched. Memory Read Multiple - Bits [21:20] offset 40h and bits [5:4] offset 40h control the mode of prefetching for memory read multiple transactions in the prefetchable range on the secondary and primary bus respectively. The default is a full prefetch, limited to the value set by bits [14:12] offset 40h. The default value is 512 bytes, or an entire read buffer.
4.3.1.3
PCI TO PCI-X PI7C21P100 must translate the conventional PCI memory read command to either the memory read DWORD or the memory read block PCI-X Command. If the conventional PCI memory read command targets non-prefetchable memory space, the command is translated into a memory read DWORD. In any other instance, the conventional PCI memory read command gets translated into a memory read block PCI-X command. Bits [25:24] offset 40h and bits [9:8] offset 40h control the mode of prefetching for memory read transactions in the prefetchable range on the secondary and primary bus respectively. The default is up to one cache line will be prefetched. The default is up to one cache line will be prefetched. PI7C21P100 translates the conventional PCI memory read line command to the memory read block PCI-X command. Bits [23:22] offset 40h and bits [7:6] offset 40h control the mode of prefetching for memory read line transactions in the prefetchable range on the secondary and primary bus respectively. The default is up to one cache line will be prefetched.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION PI7C21P100 must translate the conventional PCI memory read multiple command to the memory read block PCI-X command. Bits [21:20] offset 40h and bits [5:4] offset 40h control the mode of prefetching for memory read multiple transactions in the prefetchable range on the secondary and primary bus respectively. The default is a full prefetch, limited to the value set by bits [14:12] offset 40h. The default value is 512 bytes, or an entire read buffer. Using a value greater than this is possible, but it may be constrained by the setting of the split transaction commitment limit value in the upstream or downstream split transaction register, since the target bus is in PCI-X mode. Data fetching operations will be disconnected at all 1MB boundaries.
4.3.1.4
PCI-X TO PCI PI7C21P100 translates PCI-X memory read DWORD commands into conventional PCI memory read commands. PI7C21P100 translates a PCI-X memory read block command into one of three conventional PCI memory read commands based on the byte count and starting address. If the starting address and byte count are such that only a single DWORD (or less) is being read, the conventional PCI transaction uses the memory read command. If the PCI-X transaction reads more than one DWORD, but does not cross a cache line boundary (indicated by the Cache Line Size register in the conventional Configuration Space header), the conventional transaction uses the memory read line command. If the PCI-X transaction crosses a cache line boundary, the conventional transaction uses the memory read multiple command. If a disconnect occurs before the byte count of the PCI-X memory read block command is exhausted, the PI7C21P100 continues to issue the command until all the bytes in the count are received. PI7C21P100 disconnects once the buffer is filled and prefetches more data as 128-byte sectors of the buffer become free when split completion data is returned to the originator, until the byte count is exhausted.
4.3.2
I/O READ
The I/O Read command is not translated and fetches a DWORD of data. The command will either be split in the PCI-X mode or delayed in the conventional PCI mode.
4.3.3
4.3.3.1
CONFIGURATION READ
TYPE 1 CONFIGURATION READ The Type 1 configuration read command is only accepted on the primary interface. The command will either be split in the PCI-X mode or delayed in the conventional PCI mode.
4.3.3.2
TYPE 0 CONFIGURATION READ The Type 0 configuration read command is accepted on either the primary or secondary interface. The command returns immediate data on the primary interface regardless of the interface mode. On the secondary interface the command is treated either as a split transaction in PCI-X mode or as a delayed transaction in the PCI mode.
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4.3.4
NON-PREFETCHABLE AND DWORD READS
A non-prefetchable read transaction is a read transaction in which PI7C21P100 requests exactly one DWORD from the target and disconnects the initiator after delivering that one DWORD of read data. Unlike prefetchable read transactions, PI7C21P100 forwards the read byte enable information for the data phase. Non-prefetchable behavior is used for I/O, configuration, memory read transactions that fall into the nonprefetchable memory space for PCI mode, and all DWORD read transactions in PCI-X mode.
4.3.5
PREFETCHABLE READS
A prefetchable read transaction is a read transaction where PI7C21P100 performs speculative reads, transferring data from the target before it is requested from the initiator. This behavior allows a prefetchable read transaction to consist of multiple data transfers. For prefetchable read transactions, all byte enables are asserted for all data phases. Prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read transactions that fall into prefetchable memory space and are allowed to fetch more than a DWORD. The amount of data that is prefetched depends on the type of transaction and the setting of bits in the primary and secondary data buffering control registers in configuration space. The amount of prefetching may also be affected by the amount of free buffer space available in PI7C21P100, and by any read address boundaries encountered.
4.3.5.1
PCI-X TO PCI-X AND PCI-X TO PCI For PCI-X to PCI transactions, PI7C21P100 continues to generate data requests to the PCI interface and keeps the prefetch buffer full until the entire amount of data requested is transferred. For PCI-X to PCI-X transactions, the split transaction commitment limit value contained in the upstream or downstream split transaction register determines the operation. If the value is greater than or equal to the split transaction capacity (4KB) but less than 32KB, the maximum request amount is 512 bytes. Larger transfers will be decomposed into a series of smaller transfers, until the original byte count has been satisfied. If the commitment limit value indicates 32KB or more, the original request amount is used and decomposition is not performed. If the original request is broken into smaller requests the bridge waits until the previous completion has been totally received before a new request is issued. This ensures that the data does not get out of order and that two requests with the same sequence ID are not issued. In either case, the bridge generates a new requester ID for each request passed through the bridge.
4.3.5.2
PCI TO PCI The method used for transfers in PCI-to-PCI mode is user defined in the primary and secondary data buffering control registers. These registers have bits for memory read to prefetchable space, memory read line, and memory read multiple transactions. For memory read, the bits select whether to read a DWORD, read to a cache line boundary, or to fill the prefetch buffer. For memory read line and memory read multiple transactions, the bits select whether to read to a cache line boundary or to fill the prefetch buffer. In all cases, if the bits Page 28 of 77 June 10, 2005 Revision 1.06
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION are selected to fill the prefetch buffer, the maximum amount of data that is requested on the target interface is controllable by the setting of the maximum memory read byte count bits of the Primary and Secondary Data Buffering Control registers. When more than 512 bytes are requested, the bridge fetches data to fill the buffer and then fetches more data to keep the buffer filled as sectors (128 bytes) are emptied and become free to use again.
4.3.5.3
PCI TO PCI-X The method used for transfers in the PCI to PCI-X mode is similar to transfers in the PCI-toPCI mode, except that the maximum request amount may be additionally constrained by the setting of the split transaction commitment limit value in the upstream or downstream split transaction register. The only other difference is that prefetching will not stop when the originating master disconnects. Prefetching will only stop when all of the requested data is received.
4.3.6
DYNAMIC PREFETCH (CONVENTIONAL PCI MODE ONLY)
For prefetchable reads described in the previous section, the prefetching length is normally predefined and cannot be changed once it is set. This may cause some inefficiency as the prefetching length determined could be larger or smaller than the actual data being prefetched. To make prefetching more efficient, PI7C21P100 incorporates dynamic prefetching control logic. This logic regulates the different PCI memory read commands (MR - memory read, MRL - memory read line, and MRM - memory read multiple) to improve memory read burst performance. PI7C21P100 tracks every memory read burst transaction and tallies the status. By using the status information, PI7C21P100 can determine to increase, reduce, or keep the same cache line length to be prefetched. Over time, PI7C21P100 can better match the correct cache line setting to the length of data being requested. The dynamic prefetching control logic is set with bits[3:2] offset 48h.
4.4
CONFIGURATION TRANSACTIONS
Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed by configuration commands. All registers are accessible in configuration space only. In addition to accepting configuration transactions for initialization of its own configuration space, the PI7C21P100 also forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle generation. To support hierarchical PCI bus systems, two types of configuration transactions are specified: Type 0 and Type 1. Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to 00b. Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and the lowest two address bits set to 01b. Page 29 of 77 June 10, 2005 Revision 1.06
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION The register number is found in both Type 0 and Type 1 formats and gives the DWORD address of the configuration register to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of a multifunction device is to be accessed. For single-function devices, this value is not decoded. The addresses of Type 1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction is targeted.
4.4.1
TYPE 0 ACCESS TO PI7C21P100
The configuration space is accessed by a Type 0 configuration transaction. The configuration space can be accessed from the primary or secondary interface. S_IDSEL should be tied LOW if access is not required from the secondary interface. On the primary interface, PI7C21P100 responds to a Type 0 configuration transaction by accepting the transaction when the following conditions are met during the address phase: P_CBE[3:0]# indicates a configuration write or configuration read transaction The two lowest address bits on P_AD[1:0] are 00 P_IDSEL is asserted Bit[2] offset 44h (Miscellaneous Control Register) is 0 On the secondary interface, PI7C21P100 responds to a Type 0 configuration transaction by accepting the transaction when the following conditions are met during the address phase: S_CBE[3:0]# indicates a configuration write or configuration read transaction The two lowest address bits on S_AD[1:0] are 00 S_IDSEL is asserted The function number is not decoded since the bridge is a single-function device. All configuration transactions to the bridge are handled as DWORD operations.
4.4.2
TYPE 1 TO TYPE 0 CONVERSION
Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI/PCI-X bus system. A bridge is the only type of device that should respond to a Type 1 configuration command. Type 1 configuration commands are used when the configuration access is intended for a PCI/PCI-X device that resides on a bus other than the one where the Type 1 transaction is generated. PI7C21P100 performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary interface and is intended for a device attached directly to the secondary interface. PI7C21P100 must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction. PI7C21P100 responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the secondary interface when the following conditions are met during the address phase: The lowest two address bits on P_AD[1:0] are 01b. Page 30 of 77 June 10, 2005 Revision 1.06
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION The bus number in address field P_AD[23:16] is equal to the value in the secondary bus number register in configuration space. P_CBE[3:0]# is a configuration read or configuration write transaction. When PI7C21P100 translates the Type 1 transaction to a Type 0 transaction on the secondary interface, it performs the following translations to the address: Sets the lowest two address bits on S_AD[1:0] to 00. Decodes the device number and drives the bit pattern specified in Table 4-4 on S_AD[31:16] for the purpose of asserting the device's IDSEL signal. Sets S_AD[15:11] to 0 if the secondary bus is operating in conventional PCI mode (device number is passed through unchanged in PCI-X mode) Leaves unchanged the function number and register number fields. PI7C21P100 asserts a unique address line based on the device number. These address lines may be used as secondary bus IDSEL signals. The mapping of the address lines depends on the device number in the address bits P_AD[15:11] for Type 1 transactions. Table 4-4 presents the mapping that PI7C21P100 uses. Table 4-4 DEVICE NUMBER TO IDSEL
Device Number 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h - 1Eh 1Fh P_AD[15:11] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 - 11110 11111 Secondary IDSEL S_AD[31:16] 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 or, may convert to a special cycle transaction described in section 4.4.4
PI7C21P100 forwards Type 1 to Type 0 configuration read or write transactions as delayed transactions in PCI mode or as split transactions in PCI-X mode.
4.4.3
TYPE 1 TO TYPE 1 FORWARDING
Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCI-to-PCI bridges are used. When PI7C21P100 detects a Type 1 configuration transaction intended for a PCI/PCI-X bus downstream from the secondary interface, PI7C21P100 forwards the transaction unchanged to the secondary interface. Ultimately, this transaction is translated to a Type 0 configuration command or to a special cycle transaction by a downstream PCI bridge. Downstream Type 1 to Type 1 forwarding occurs when the following conditions are met during the address phase:
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION The lowest two address bits on P_AD[1:0] are equal to 01b. The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. P_AD[1:0] is a configuration read or configuration write transaction. PI7C21P100 also supports Type 1 to Type 1 forwarding of configuration write transactions upstream to support upstream special cycle generation. All upstream Type 1 configuration read commands are ignored by PI7C21P100. PI7C21P100 forwards Type 1 to Type 1 configuration read and write transactions as delayed transactions in the PCI mode and as split transactions in PCI-X mode.
4.4.4
SPECIAL CYCLES
The Type 1 configuration mechanism is used to generate special cycle transactions in hierarchical PCI/PCI-X systems. Special cycle transactions can be generated from Type 1 configuration write transactions in either the upstream or the downstream direction. PI7C21P100 initiates a special cycle on the target bus when a Type 1 configuration write transaction is detected on the initiating bus and the following conditions are met during the address phase: The lowest two address bits on AD[1:0] are equal to 01b. The device number in address bits AD[15:11] is equal to 11111b. The function number in address bits AD[10:8] is equal to 111b. The register number in address bits AD[7:2] is equal to 000000b. The bus number is equal to the value in the secondary bus number register for downstream transactions or equal to the value in the primary bus number register for upstream transactions. The bus command on CBE is a configuration write command. When PI7C21P100 initiates the transaction on the target interface, the bus command is changed from configuration write to special cycle. Devices that use special cycles ignore the address and decode only the bus command. The data phase contains the special cycle message. The transaction is forwarded as a delayed transaction in PCI mode and as a split transaction in PCI-X mode. Once the transaction is completed on the target bus through detection of the master abort condition, PI7C21P100 completes the transaction on the initiating bus by accepting the retry on the delayed command in PCI mode or by generating a completion message in PCI-X mode. Special cycles received by PI7C21P100 as a target are ignored.
5
TRANSACTION ORDERING
To maintain data coherency and consistency, PI7C21P100 complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.2 for PCI mode, and PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a for PCI-X mode. This chapter describes the ordering rules that control transaction forwarding across PI7C21P100.
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5.1
GENERAL ORDERING GUIDELINES
Independent transactions on primary and secondary buses have a relationship only when those transactions cross PI7C21P100. The following general ordering guidelines govern transactions crossing PI7C21P100: Requests terminated with target retry can be accepted and completed in any order with respect to other transactions that have been terminated with target retry. If the order of completion of delayed or split requests is important, the initiator should not start a second delayed or split transaction until the first one has been completed. If more than one delayed or split transaction is initiated, the initiator should repeat all retried requests, using some fairness algorithm. Repeating a delayed or split transaction cannot be contingent on completion of another delayed transaction. Otherwise, a deadlock can occur. Write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. PI7C21P100 can accept posted write transactions on both interfaces at the same time, as well as initiate posted write transactions on both interfaces at the same time. The acceptance of a posted memory or memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. This is true for PI7C21P100 and must also be true for other bus agents. Otherwise, a deadlock can occur. PI7C21P100 accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across PI7C21P100.
5.2
ORDERING RULES
Table 5-1 SUMMARY OF TRANSACTION ORDERING IN PCI MODEand Table 5-2 show the ordering relationships of all the transactions and refers by number to the ordering rules that follow. Table 5-1 SUMMARY OF TRANSACTION ORDERING IN PCI MODE
Pass Delayed Delayed Delayed Delayed Read Write Read Write Request Request Completion Completion Posted Write No Yes Yes Yes Yes Delayed Read Request No Yes Yes Yes Yes Delayed Write Request No Yes No Yes Yes Delayed Read Completion No1 Yes Yes Yes Yes Delayed Write Completion No Yes Yes Yes No 1. If the relaxed ordering bit is set in PCI to PCI mode, or the enable relaxed ordering bit in the primary and/or secondary data buffering control registers is set in any other mode, read completions can pass memory writes. Posted Write
Table 5-2 SUMMARY OF TRANSACTION ORDERING IN PCI-X MODE
Pass Posted Write Delayed Read Request Delayed Write Request Memory Write No No No Split Read Request Yes Yes Yes Split Write Request Yes Yes No Split Read Completion Yes Yes Yes Split Write Completion Yes Yes Yes
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Memory Split Read Split Write Split Read Split Write Write Request Request Completion Completion Delayed Read Completion No1 Yes Yes Yes2 Yes Delayed Write Completion No Yes Yes Yes No 1. If the relaxed ordering bit is set in PCI-X to PCI-X mode, or the enable relaxed ordering bit in the primary and/or secondary data buffering control registers is set in any other mode, read completions can pass memory writes. 2. Split Read Completions with the same sequence ID must remain in address order. Pass
6
CLOCKS
This chapter provides information about the clocks.
6.1
PRIMARY AND SECONDARY CLOCK INPUTS
The primary and secondary interface on PI7C21P100 each has its own clock input pin. P_CLK is the clock input for the primary and S_CLK is the input for the secondary (S_CLK also controls the internal arbiter). The two clocks are independent of each other and may be run synchronously or asynchronously to each other at any value supported by the PCI or PCIX specifications. Each interface utilizes a separate internal PLL (phase-locked loop) circuit when running in PCI-X mode. In PCI mode, the PLL's are bypassed, allowing for any clock frequency from 0 to 66MHz. If the primary is running at 133MHz in PCI-X mode, then the secondary is limited to a minimum frequency of 33MHz in conventional PCI mode. To run the secondary slower, the primary frequency needs to be reduced so that the ratio does not exceed 4:1.
6.2
CLOCK JITTER
PI7C21P100 tolerates a maximum of +/- 250ps of short term and long term jitter on the clock inputs. Short term jitter is defined as the relationship between one clock edge to the next subsequent clock edge for one clock cycle, and long term jitter is the same relationship over many clock cycles.
6.3
6.3.1
MODE AND CLOCK FREQUENCY DETERMINATION
PRIMARY BUS
PI7C21P100 does not have I/O pins for the M66EN or PCIXCAP signals on the primary bus. PI7C21P100 adjusts its internal configuration based on the initialization pattern it detects on P_DEVSEL#, P_STOP#, and P_TRDY# at the rising edge of P_RST#. If the internal PLL is being used (the bus is configured in the PCI-X mode), a maximum of 100s from the rising edge of P_RST# is required to lock the PLL to the frequency of the clock supplied on the P_CLK input.
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6.3.2
SECONDARY BUS
The secondary interface is capable of operating in either conventional PCI mode or in PCI-X mode. PI7C21P100 controls the mode and frequency for the secondary bus by utilizing a pullup circuit connected to S_PCIXCAP. There are two pull-up resistors in the circuit as recommended by the PCI-X addendum. The first resistor is a weak pull-up (56K ohms) whose value is selected to set the voltage of S_PCIXCAP below its low threshold when a PCI-X 66 device is attached to the secondary bus. The second resistor is a strong pull-up, externally wired between S_PCIXCAP and S_PCIXCAP_PU. The value of the resistor (1K ohm) is selected to set the voltage of S_PCIXCAP above its high threshold when all devices on the secondary are PCI-X 66 capable. To detect the mode and frequency of the secondary bus, S_PCIXCAP_PU is initially disabled and PI7C21P100 samples the value on S_PCIXCAP. If PI7C21P100 sees a logic LOW on S_PCIXCAP, one or more devices on the secondary have either pulled the signal to ground (PCI-X 66 capable) or tied it to ground (only capable of conventional PCI mode). To differentiate between the two conditions, PI7C21P100 then enables S_PCIXCAP_PU to put the strong pull-up into the circuit. If S_PCIXCAP remains at a logic LOW, it must be tied to ground by one or more devices, and the bus is initialized to conventional PCI mode. If S_PCIXCAP_PU can be pulled up, one or more devices are capable of only PCI-X 66 operation so the bus is initialized to PCI-X 66 mode. If PI7C21P100 sees a logic HIGH on S_PCIXCAP, then all devices on the secondary bus are capable of PCI-X 133 operation. PI7C21P100 then samples S_SEL100 to distinguish between the 66-100 MHz and the 100-133 MHz clock frequency ranges. If PI7C21P100 sees logic HIGH on S_SEL100, the secondary bus is initialized to PCI-X 100 mode. If the value is LOW, PCI-X 133 is initialized. These two ranges allow adjustment of the clock frequency to account for bus loading conditions. There is no pin for M66EN for the secondary interface on PI7C21P100 because the internal PLL is bypassed in conventional PCI mode. S_CLK is used directly, eliminating the need to distinguish between conventional PCI 33 and conventional PCI 66. Table 6-1 PROGRAMMABLE PULL-UP CIRCUIT
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6.3.3
CLOCK STABILITY
To comply with PCI and PCI-X architecture specifications, the bus clock must be stable and running at the designated frequency for at least 100us after deassertion of the bus reset. S_CLK_STABLE is used to determine and detect when S_CLK has become stable. During a bus reset, PI7C21P100 will wait for the assertion of S_CLK_STABLE before determining the mode and frequency. PI7C21P100 is expecting no more than one transition on the S_CLK_STABLE input from the "not stable" to the "stable" state. S_CLK_STABLE input may be tied HIGH if the secondary clock input is known to be always stable prior to the deassertion of the primary bus reset signal or the secondary bus reset bit of the bridge control register. Examples of sources for S_CLK_STABLE are lock indicators on circuits that employ PLL's or "power good" indicators.
6.3.4
DRIVER IMPEDANCE SELECTION
The output drivers on PI7C21P100 are capable of two different output impedances, 40 ohm output impedance and a 20 ohm. The output impedance for the primary and secondary interfaces is separately controlled. PI7C21P100 selects a default impedance value at the deassertion of the bus reset based on the bus mode and frequency. If a bus is configured to be in PCI-X 133 mode, it is assumed that the bus will have fewer devices and have a higher impedance. In this case, the drivers utilize the 40 ohm output impedance mode. The 20 ohm output impedance mode is utilized for all other PCI-X and all PCI configurations, assuming that the bus is more heavily loaded and has lower impedance. Some applications do not follow these assumptions so two control signals are provided; P_DRVR for the primary and S_DRVR for the secondary. When these inputs are pulled HIGH, PI7C21P100 will change the output impedance of the drivers on their respective interfaces to the opposite state than was assumed by default, as shown in Table 6-2. The driver mode may not be changed dynamically, but can be changed during each bus reset. Table 6-2 DRIVER IMPEDANCE SELECTION
Primary Bus Mode Conventional PCI PCI-X 66 PCI-X 100 PCI-X 133 Default Driver Mode (P_DRVR=0) 20 ohm 20 ohm 20 ohm 20 ohm Driver Mode if (P_DRVR=1) 40 ohm 40 ohm 40 ohm 20 ohm Secondary Bus Mode Conventional PCI PCI-X 66 PCI-X 100 PCI-X 133 Default Driver Mode (S_DRVR=0) 20 ohm 20 ohm 20 ohm 40 ohm Driver Mode if (S_DRVR=1) 40 ohm 40 ohm 40 ohm 20 ohm
7
RESET
The primary and secondary interface each have their own asynchronous reset signal used at power-on and at other times to put PI7C21P100 into a known state. The reset signal on the primary (P_RST#) is an input pin, while the reset signal on the secondary (S_RST#) is an output pin driven by PI7C21P100.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
7.1
PRIMARY INTERFACE RESET
When P_RST# is asserted, the following events occur: PI7C21P100 immediately tri-states all primary PCI interface signals. S_AD[31:0] and S_CBE[3:0] are driven LOW on the secondary interface and other control signals are tristated. PI7C21P100 performs a chip reset. Registers that have default values are reset. PI7C21P100 is not accessible during P_RST#. After P_RST# is deasserted in PCI-X mode, PI7C21P100 remains inaccessible for 100us to enable the internal PLL to lock to its target frequency. In conventional PCI mode, PI7C21P100 is held in reset 7 PCI clocks after the deassertion of P_RST#.
7.2
SECONDARY INTERFACE RESET
PI7C21P100 is responsible for driving the secondary bus reset signals, S_RST#. PI721P100 asserts S_RST# when any of the following conditions are met: Signal P_RST# is asserted. Signal S_RST# remains asserted as long as P_RST# is asserted and does not de-assert until P_RST# is de-asserted. The secondary reset bit in the bridge control register is set. Signal S_RST# remains asserted until a configuration write operation clears the secondary reset bit. Several things must occur at or prior to the de-assertion of S_RST#. Once P_RST# is de-asserted or the secondary bus reset bit is changed from 1 to 0, PI7C21P100 will wait for the S_CLK_STABLE signal to be asserted before proceeding. S_CLK must be stable at a frequency within the bus capability limits prior to the assertion of S_CLK_STABLE. Since the PCI Local Bus Specification requires that the bus clock be stable for at least 100us prior to the de-assertion of the bus reset, S_CLK_STABLE serves as a gate to a timer that ensures that this requirement is met. During this time delay period, the secondary bus mode and frequency is determined through the programmable pull-up circuit. This process may include up to 80us for the capacitive load on S_PCIXCAP to be charged. By the time the 100us timer expires, the bus mode and frequency will have been determined. The S_RST# signal is then de-asserted a minimum of ten secondary bus PCI clock cycles later. When the secondary bus is operating in PCI-X mode, an internal PLL is used to source the clock tree for the secondary clock domain inside PI7C21P100. The appropriate range and tuning bits for the PLL are set once the mode and frequency are determined, and an internal PLL reset signal is deactivated to allow the PLL to begin locking to the S_CLK input frequency. The PLL requires an allowance of 100us to accomplish this frequency lock. An internal reset is held on the logic in the secondary clock domain until this time period has elapsed. While the internal reset is active, PI7C21P100 will not respond to any secondary bus transactions. When the secondary bus is operating in PCI mode, the internal PLL for the secondary interface is not used. The internal PLL reset remains activated, keeping the PLL in the bypass mode, and the internal logic reset is held for 5 additional secondary PCI clock cycles.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION Table 7-1 DELAY TIMES FOR DE-ASSERTION OF S_RST#
PCI-X 66 PCI-X 100 PCI-X 133 6678 primary clock 13350 primary 13350 primary cycles clock cycles clock cycles 100us - 133us 133us - 200us 100us - 133us 6675 primary clock 6675 primary clock 13347 primary 13347 primary TXCAP cycles cycles clock cycles clock cycles 100us - 133us 133us - 200us 100us - 133us 11 secondary and 7 11 secondary and 7 11 secondary and 7 11 secondary and 7 TSRSTDLY primary clock primary clock primary clock primary clock cycles cycles cycles cycles 16 secondary clock 6687 secondary 13350 secondary 13350 secondary TSIRSTDLY cycles clock cycles clock cycles clock cycles 100us - 133us 133us - 200us 100us - 133us Note: Primary and secondary clock cycles refer to clock cycles whose period is determined by the P_CLK and S_CLK inputs. TPIRSTDLY Conventional PCI 7 primary clock cycles
Table 7-2 DE-ASSERTION OF S_RST#
7.3
BUS PARKING & BUS WIDTH DETERMINATION
Bus parking refers to driving the AD[31:0], CBE[3:0], and PAR lines to a known value while the bus is idle. In general, the device implementing the bus arbiter is responsible for parking the bus or assigning another device to park the bus. A device parks the bus when the bus is idle, its bus grant is asserted, and the device's request is not asserted. The AD[31:0], CBE[3:0], and PAR signals are driven LOW after assertion of S_RST#. PI7C21P100 will assert S_REQ64# for at least 10 PCI clock cycles to allow devices to determine whether they are connected on a 64-bit bus or 32-bit bus.
7.4
SECONDARY DEVICE MASKING
Secondary devices can be masked through configuration or power strapping of the secondary bus private device mask register. The process of converting Type 1 configuration transactions to Type 0 configuration transactions is modified by the contents of the secondary bus private device mask register. A configuration transaction that targets a device masked by this register is routed to device 15. Secondary bus architectures which are designed to support masking of Page 38 of 77 June 10, 2005 Revision 1.06
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION devices should not implement a device number 15 (i.e., S_AD(31)). The device mask bit options (device numbers 1, 4, 5, 6, 7, 9, and 13) defined by PI7C21P100 allow architectures to support private device groupings that use a single or multiple interrupt binding.
7.5
ADDRESS PARITY ERRORS
PI7C21P100 checks address parity for all transactions on both buses, for all address and all bus commands. When PI7C21P100 detects an address parity error, the transaction will not be claimed and will be allowed to terminate with a master abort. The result of an address parity error will be controlled by the parity error response bits in both the command and bridge control registers.
7.6
OPTIONAL BASE ADDRESS REGISTER
The 64 bit Base Address register located in the configuration register at offsets 10h and 14h can optionally be used to acquire a 1 MB memory region at system initialization. PI7C21P100 uses this register to claim an additional prefetchable memory region for the secondary bus. When used with the secondary device masking, this allows for the acquisition of memory space for private devices that are not otherwise viewable by the system software. This 64 bit base address register and the memory space defined by it are enabled by the BAR_EN. When BAR_EN is pulled LOW, this register location returns zeros for reads and cannot be written. When BAR_EN is pulled HIGH, the upper memory base address register and lower memory base address registers combined specify address bits 63:20 of a memory region. Memory accesses on the primary bus are compared against this register, if address bits 63:20 are equal to bits 63:20 of the address defined by the combination of the lower memory base address register and the upper memory base address register, the access is claimed by PI7C21P100 and passed through to the secondary bus. Memory accesses on the secondary bus are also compared against this register, if address bits 63:20 are equal to bits 63:20 of the address defined by the combination of the lower memory base address register and the upper memory base address register, the access is ignored by the bridge.
7.7
OPTIONAL CONFIGURATION ACCESS FROM THE SECONDARY BUS
PI7C21P100 accepts Type 0 configuration transactions when the following conditions are met during the address phase: S_CBE[3:0]# indicates a configuration read or configuration write transaction S_AD[1:0] are 00 S_IDSEL is asserted Applications that require access to the bridge configuration registers via the secondary bus may control the initialization sequence through the P_CFG_BUSY pin and bit[2] offset 44h of the miscellaneous control register. When P_CFG_BUSY is pulled HIGH, bit[2] offset 44h is set to 1b at power up and reset. This causes PI7C21P100 to retry Type 0 configuration transactions on the primary bus that would otherwise be accepted. PI7C21P100 continues to retry these transactions until bit[2] offset 44h is set to 0b by a configuration write initiated on the secondary bus. This allows a device on the secondary bus to initialize the bridge and any private devices on the secondary bus without contention from devices accessing the bridge Page 39 of 77 June 10, 2005 Revision 1.06
PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION through the primary bus. Applications that do not require access to the bridge configuration registers via the secondary bus should pull both the S_IDSEL and P_CFG_BUSY pins LOW.
7.8
SHORT TERM CACHING
Short Term Caching is a means to provide performance improvements where upstream devices are not able to stream data continuously to meet the prefetching needs of the PI7C21P100. When the master completes the transaction, the bridge is required to discard the balance of any data that was prefetched for the master. To prevent performance impacts when dealing with target devices that can only stream data of 128 to 512 bytes before disconnecting, PI7C21P100 utilizes Short Term Caching. This feature applies only when the secondary bus is operating in conventional PCI mode and provides a time limited read data cache in which the bridge will not discard prefetched read data after the request has been completed on the initiating bus. Short Term Caching is an optional feature which is enabled by setting bit[8] and bit[15] offset B8h of the Miscellaneous Control Register 2. When enabled, PI7C21P100 will not discard the additional prefetched data when the read transaction has been completed on the initiating bus. PI7C21P100 will continue to prefetch data up to the amount specified by bits [30:28] offset 40h of the Secondary Data Buffering Control Register. Should the initiator generate a new transaction requesting the previously prefetched data, PI7C21P100 will return that data. PI7C21P100 will discard the data approximately 64 secondary clocks after some of the data for a request has been returned to the initiator, and the initiator has not requested additional data. This feature applies to all secondary devices if enabled. System designers need to ensure that all attached devices have memory region(s) that are architected to be accessed by only one master and that the additional prefetching will present data to the initiator in the same state as if the initial transaction were continued. This feature should only be used in system designs that are able to ensure that the data provided to the master has not been modified since the initial transaction.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8
CONFIGURATION REGISTERS
PCI configuration defines a 64 DWORD space to define various attributes of PI7C21P100.
8.1
CONFIGURATION REGISTER SPACE MAP
Table 8-1 CONFIGURATION SPACE MAP
Bit Number 31 - 24 Device ID Primary Status 23 - 16 15 - 8 7-0 Vendor ID Primary Command Class Code Revision ID BIST Header Type Primary Latency Timer Cache Line Size Lower Memory Base Address Upper Memory Base Address Secondary Latency Subordinate Bus Secondary Bus Number Primary Bus Number Timer Number Secondary Status I/O Limit I/O Base Memory Limit Memory Base Prefetchable Memory Limit Prefetchable Memory Base Prefetchable Base Upper 32-bit Prefetchable Limit Upper 32-bit I/O Limit Upper 16-bit I/O Base Upper 16-bit Reserved Capability Pointer Expansion ROM Base Address Bridge Control Interrupt Pin Interrupt Line Secondary Data Buffering Control Primary Data Buffering Control Reserved Miscellaneous Control Reserverd Extended Chip Control Extended Chip Control 2 1 Reserved Reserved Arbiter Mode Reserved Arbiter Enable Reserved Arbiter Priority Reserved SERR# Disable Primary Retry Counter Secondary Retry Counter Reserved Discard Timer Control Reserved Retry and Timer Status Reserved Opaque Memory Enable Opaque Memory Limit Opaque Memory Base Opaque Memory Base Upper 32-bit Opaque Memory Limit Upper 32-bit PCI-X Secondary Status Next Capability Pointer PCI-X Capability ID PCI-X Bridge Status Secondary Bus Upstream Split Transaction Primary Bus Downstream Split Transaction Power Management Capabilities Next Capabilities Power Management ID Pointer PCI-to-PCI Bridge Support Extension Power Management Control and Status Reserved Secondary Bus Private Device Mask Reserved Reserved Miscellaneous Control 2 Reserved DWORD Address 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h 94h 98h-Ach B0h B4h B8h BCh-FFh
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION 8.1.1.1 SIGNAL TYPE DEFINITION
SIGNAL TYPE RO RW RWC DEFINITION READ ONLY READ / WRITE READ / WRITE 1 TO CLEAR
8.1.2
VENDOR ID REGISTER - OFFSET 00h
BIT 15:0 FUNCTION Vendor ID TYPE RO DESCRIPTION Identifies Pericom as the vendor of this device. Hardwired as 12D8h
8.1.3
DEVICE ID REGISTER - OFFSET 00h
BIT 31:16 FUNCTION Device ID TYPE RO DESCRIPTION Identifies the device as PI7C21P100. Hardwired as 01A7h.
8.1.4
COMMAND REGISTER - OFFSET 04h
BIT 15:10 9 FUNCTION Reserved Fast Back-to-Back Enable P_SERR# Enable TYPE RO RO DESCRIPTION Reserved. Returns 000000 when read. Fast Back-to-Back Control 0: Prohibits PI7C21P100 to initiate fast back-to-back transactions on the primary This bit is ignored in PCI-X mode. Reset to 0 System Error Control 0: Disables the P_SERR# driver on the primary 1: Enables the P_SERR# driver on the primary Reset to 0 Wait Cycle Control 0: Address/data stepping is disabled (primary and secondary) This bit is ignored in PCI-X mode. Returns 0 when read. Parity Error Response 0: PI7C21P100 may ignore any detected parity errors and continue normal operation 1: PI7C21P100 must take its normal action when a parity error is detected. Reset to 0 VGA Palette Snoop Control 0: Ignore VGA palette accesses on the primary 1: Enables positive decoding response to VGA palette writes on the primary with I/O address bits AD[9:0] equal to 3C6h, 3C8h, and 3C9h (inclusive of ISA aliases; AD[15:10] are not decoded and may be any value. Reset to 0 Memory Write and Invalidate Control 0: Disables Memory Write and Invalidate transactions. PI7C21P100 does not generate memory write and invalidate transactions. This bit is ignored in PCI-X mode. Returns 0 when read. Special Cycle Control 0: PI7C21P100 does not respond as a target to Special Cycle transactions. Returns 0 when read.
8
RW
7 6
Wait Cycle Control Parity Error Response
RO RW
5
VGA Palette Snoop Enable
RW
4
Memory Write and Invalidate Enable Special Cycle Enable
RO
3
RO
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
BIT 2 FUNCTION Bus Master Enable TYPE RW DESCRIPTION Bus Master Control 0: PI7C21P100 does not initiate memory and I/O transactions on the primary and disables responses to memory and I/O transactions on the secondary 1: Enables PI7C21P100 to operate as a master on the primary for memory and I/O transactions forwarded from the secondary. In PCI-X mode, PI7C21P100 is allowed to initiate a split completion transaction regardless of the status of this bit. Reset to 0 Memory Space Control 0: Ignore memory transactions on the primary 1: Enables responses to memory transactions on the primary Reset to 0 I/O Space Control 0: Ignores I/O transactions on the primary 1: Enables responses to I/O transaction on the primary Reset to 0
1
Memory Space Enable
RW
0
I/O Space Enable
RW
8.1.5
PRIMARY STATUS REGISTER - OFFSET 04h
BIT 31 FUNCTION Detected Parity Error TYPE RWC DESCRIPTION Detected Parity Error Status 0: Address or data parity error not detected by PI7C21P100 1: Address or data parity error detected by PI7C21P100 Reset to 0 Signaled System Error Status 0: PI7C21P100 did not assert SERR# 1: PI7C21P100 asserted SERR# Reset to 0 Received Master Abort Status 0: Transaction not terminated with a bus master abort 1: Transaction terminated with a bus master abort Reset to 0 Received Target Abort Status 0: Transaction not terminated with a target abort 1: Transaction terminated with a target abort Reset to 0 Signaled Target Abort Status 0: Target device did not terminate transaction with a target abort 1: Target device terminated transaction with a target abort DEVESEL# Timing Status 01: Medium decoding. Returns 01h when read. Data Parity Error Status 0: No data parity error detected 1: Data parity error detected Reset to 0 Fast Back-to-Back Status 0: Target not capable of decoding fast back-to-back transactions in PCI-X mode 1: Target capable of decoding fast back-to-back transactions in conventional PCI mode Returns 0 in PCI-X mode and 1 in conventional PCI mode Reserved. Returns 0 when read. 66MHz Capable Status 1: Capable of 66MHz operation Returns 1 when read. Capability List 1: PI7C21P100 supports the capability list and offset 34h is the pointer to the data structure. Returns 0 when read. Reserved. Returns 0000 when read.
30
Signaled System Error
RWC
29
Received Master Abort
RWC
28
Received Target Abort
RWC
27 26:25 24
Signaled Target Abort DEVSEL# Timing Data Parity Error
RWC RO RWC
23
Fast Back-to-Back Capable
RO
22 21 20
Reserved 66MHz Capable Capability List
RO RO RO
19:16
Reserved
RO
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.6
REVISION ID REGISTER - OFFSET 08h
BIT 7:0 FUNCTION Revision ID TYPE RO DESCRIPTION Specifies the revision of PI7C21P100. Read as 0h
8.1.7
CLASS CODE REGISTER - OFFSET 08h
BIT 31:24 23:16 15:8 FUNCTION Class Code Sub Class Code Programming Interface TYPE RO RO RO DESCRIPTION Specifies the base class code for PI7C21P100 identifying it as a Bridge device according to PCI specifications. Read as 06h Specifies the sub-class code identifying PI7C21P100 as a Bridge device. Read as 04h. Subtractive decoding not supported. Read as 0h
8.1.8
CACHE LINE SIZE REGISTER - OFFSET 0Ch
BIT 7:0 FUNCTION Cache Line Size TYPE RW DESCRIPTION Designates the cache line size for the system and is used when terminating memory write and invalidate transactions and when prefetching memory read transactions. Not used in PCI-X mode. bit[7:6]: Not supported and should be 00b bit[5]: If 1, then cache line size = 32 DWORDS bit[4]: If 1, then cache line size = 16 DWORDS bit[3]: If 1, then cache line size = 8 DWORDS bit[2]: If 1, then cache line size = 4 DWORDS bit[1:0]: Not supported and should be 00b
8.1.9
PRIMARY LATENCY TIMER - OFFSET 0Ch
BIT 15:11 10:8 FUNCTION Primary Latency Timer Primary Latency Timer TYPE RW RO DESCRIPTION Designates the upper 5 bits of the primary latency timer in PCI clock units Designates the lower 3 bits of the primary latency timer in PCI clock units. Returns 000 when read to force 8-cycle increments for the latency timer.
8.1.10
HEADER TYPE REGISTER - OFFSET 0Ch
BIT 23 22:16 FUNCTION Single Function Device PCI-to-PCI Configuration TYPE RO RO DESCRIPTION Returns 0 when read to designate single function device Returns 0000001 when read.
8.1.11
BIST REGISTER - OFFSET 0Ch
BIT 31:24 FUNCTION BIST TYPE RO DESCRIPTION BIST not supported. Returns 0 when read.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.12
LOWER MEMORY BASE ADDRESS REGISTER - OFFSET 10h
BIT 31:20 19:4 3 2:1 0 FUNCTION Memory Base Address Reserved Prefetchable Indicator Decoder Width Decoder Type TYPE RW RO RO RO RO DESCRIPTION Address bits[31:20] of the memory base address if BAR_EN is 1. If BAR_EN is 0, then this register is reserved and returns zeros when read. Reserved. Returns 00h when read Identifies the address range defined by this register is prefetchable. Returns 1 when read Indicates that this is the lower portion of a 64-bit register. Returns 10b when read. Indicates that this register is a memory decoder. Returns 0 when read.
8.1.13
UPPER MEMORY BASE ADDRESS REGISTER - OFFSET 14h
BIT 31:0 FUNCTION Upper Memory Base Address TYPE RW DESCRIPTION Address bits[63:32] of the memory base address if BAR_EN is 1. If BAR_EN is 0, this register is reserved and returns zeros when read.
8.1.14
PRIMARY BUS NUMBER REGISTER - OFFSET 18h
BIT 7:0 FUNCTION Primary Bus Number TYPE RW DESCRIPTION Records the bus number of the PCI segment that PI7C21P100 is connected to on the primary side. Reset to 00h
8.1.15
SECONDARY BUS NUMBER REGISTER - OFFSET 18h
BIT 15:8 FUNCTION Secondary Bus Number TYPE RW DESCRIPTION Records the bus number of the PCI segment that PI7C21P100 is connected to on the secondary side. Reset to 00h
8.1.16
SUBORDINATE BUS NUMBER REGISTER - OFFSET 18h
BIT 23:16 FUNCTION Subordinate Bus Number TYPE RW DESCRIPTION Records the highest bus number of the PCI segment that resides behind PI7C21P100. Reset to 00h
8.1.17
SECONDARY LATENCY TIMER REGISTER - OFFSET 18h
BIT 31:24 FUNCTION Secondary Latency Timer TYPE RW DESCRIPTION Specifies the value of the secondary latency timer in PCI bus clock units. Reset to 00h in conventional PCI mode Reset to 40h in PCI-X mode
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.18
I/O BASE ADDRESS REGISTER - OFFSET 1Ch
BIT 7:4 3:2 1:0 FUNCTION I/O Base Address Reserved 32-bit I/O Addressing TYPE RW RO RO DESCRIPTION Specifies the base of the I/O address range bits [15:12] and is used with the I/O limit register and I/O base upper 16 bits and I/O limit upper 16-bit registers Reserved. Returns 00b when read. Returns 01b when read to indicate PI7C21P100 supports 32-bit I/O addressing
8.1.19
I/O LIMIT REGISTER - OFFSET 1Ch
BIT 15:12 11:10 9:8 FUNCTION I/O Limit Address Reserved 32-bit I/O Addressing TYPE RW RO RO DESCRIPTION Address bits[15:12] of the limit address for the address range of I/O operations that are passed from primary to secondary Reserved. Returns 00b when read. Returns 01b when read to indicate PI7C21P100 supports 32-bit I/O addressing
8.1.20
SECONDARY STATUS REGISTER - OFFSET 1Ch
BIT 31 FUNCTION Detected Parity Error TYPE RWC DESCRIPTION Detected Parity Error Status 0: Address or data parity error not detected by PI7C21P100 on the secondary 1: Address or data parity error detected by PI7C21P100 on the secondary Reset to 0 Signaled System Error Status 0: PI7C21P100 did not assert SERR# on the secondary 1: PI7C21P100 asserted SERR# on the secondary Reset to 0 Received Master Abort Status 0: Transaction not terminated with a bus master abort on the secondary 1: Transaction terminated with a bus master abort on the secondary Reset to 0 Received Target Abort Status 0: Transaction not terminated with a target abort 1: Transaction terminated with a target abort Reset to 0 Signaled Target Abort Status 0: Target device did not terminate transaction with a target abort 1: Target device terminated transaction with a target abort Reset to 0 DEVESEL# Timing Status 01: Medium decoding. Returns 01h when read. Data Parity Error Status 0: No data parity error detected on the secondary 1: Data parity error detected on the secondary Reset to 0 Fast Back-to-Back Status 0: Target not capable of decoding fast back-to-back transactions in PCI-X mode 1: Target capable of decoding fast back-to-back transactions in conventional PCI mode Returns 0 in PCI-X mode and 1 in conventional PCI mode Reserved. Returns 0 when read.
30
Signaled System Error
RWC
29
Received Master Abort
RWC
28
Received Target Abort
RWC
27
Signaled Target Abort
RWC
26:25 24
DEVSEL# Timing Data Parity Error
RO RWC
23
Fast Back-to-Back Enable
RO
22
Reserved
RO
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
BIT 21 20:16 FUNCTION 66MHz Capable Reserved TYPE RO RO DESCRIPTION 66MHz Capable Status 1: Capable of 66MHz operation Returns 1 when read. Reserved. Returns 00000 when read.
8.1.21
MEMORY BASE REGISTER - OFFSET 20h
BIT 15:4 FUNCTION Memory Base TYPE RW DESCRIPTION Specifies the base of the memory mapped I/O address range bit[31:20] and is used with the Memory Limit register to specify a range of 32-bit addresses supported for memory mapped I/O transactions. Reset to 800h Reserved. Returns 0 when read
3:0
Reserved
RO
8.1.22
MEMORY LIMIT REGISTER - OFFSET 20h
BIT 31:20 19:16 FUNCTION Memory Limit Reserved TYPE RW RO DESCRIPTION Specifies address bits[31:20] of the limit address for the address range of memory mapped I/O operations. Reset to 000h Reserved. Returns 0 when read
8.1.23
PREFETCHABLE MEMORY BASE REGISTER - OFFSET 24h
BIT 15:4 3:0 FUNCTION Prefetchable Memory Base 64-bit Addressing TYPE RW RO DESCRIPTION Specifies address bits[31:20] of the base address for the address range of prefetchable memory operations. Reset to 800h Designates 64-bit addressing support. Returns 1h when read.
8.1.24
PREFETCHABLE MEMORY LIMIT REGISTER - OFFSET 24h
BIT 31:20 19:16 FUNCTION Prefetchable Memory Limit 64-bit Addressing TYPE RW RO DESCRIPTION Specifies address bits[31:20] of the limit address for the address range of prefetchable memory operations. Reset to 800h Designates 64-bit addressing support. Returns 1h when read.
8.1.25
PREFETCHABLE BASE UPPER 32-BIT REGISTER - OFFSET 28h
BIT 31:0 FUNCTION Prefetchable Base Upper 32-bit TYPE RW DESCRIPTION Specifies address bits[63:32] of the base address for the address range of prefetchable memory operations. Reset to 0000 0000h
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.26
PREFETCHABLE LIMIT UPPER 32-BIT REGISTER - OFFSET 2Ch
BIT 31:0 FUNCTION Prefetchable Limit Upper 32-bit TYPE RW DESCRIPTION Specifies address bits[63:32] of the limit address for the address range of prefetchable memory operations. Reset to 0000 0000h
8.1.27
I/O BASE UPPER 16-BIT REGISTER - OFFSET 30h
BIT 15:0 FUNCTION I/O Base Upper 16-bit TYPE RW DESCRIPTION Specifies address bits[31:16] of the base address for the address range of I/O operations. Reset to 0000h
8.1.28
I/O LIMIT UPPER 16-BIT REGISTER - OFFSET 30h
BIT 31:16 FUNCTION I/O Limit Upper 16-bit TYPE RW DESCRIPTION Specifies address bits[31:16] of the limit address for the address range of I/O operations. Reset to 0000h
8.1.29
CAPABILITY POINTER - OFFSET 34h
BIT 7:0 FUNCTION Capability Pointer TYPE RO DESCRIPTION Pointer to a capabilities list in the configuration space. Returns 80h when read.
8.1.30
EXPANSION ROM BASE ADDRESS REGISTER - OFFSET 38h
BIT 31:0 FUNCTION Expansion ROM Base Address TYPE RO DESCRIPTION Expansion ROM not supported. Returns 00000000h when read
8.1.31
INTERRUPT LINE REGISTER - OFFSET 3Ch
BIT 7:0 FUNCTION Interrupt Line Register TYPE RW DESCRIPTION For POST program to initialize to FFh, defining PI7C21P100 does not implement an interrupt pin.
8.1.32
INTERRUPT PIN REGISTER - OFFSET 3Ch
BIT 15:8 FUNCTION Interrupt Pin Register TYPE RO DESCRIPTION Defines the interrupt pin, but PI7C21P100 does not implement any interrupt pins. Read as 00h.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.33
BRIDGE CONTROL REGISTER - OFFSET 3Ch
BIT 31:28 27 FUNCTION RESERVED Discard Timer P_SERR# Enable TYPE RO RW DESCRIPTION Reserved. Returns 0h when read. Discard Timer P_SERR# Enable 0: Does not assert P_SERR# on the primary interface as a result of the expiration of either the primary discard timer or secondary discard timer. 1: Asserts P_SERR# on the primary interface as a result of the expiration of either the primary discard timer or secondary discard timer. This bit is ignored in PCI-X mode. Reset to 0h. Master Timeout Status 0: No discard timer error 1: Discard timer error (from primary or secondary discard timer) This bit remains 0 when in PCI-X mode. Reset to 0h. Secondary Master Timeout Status 15 0: The secondary discard timer counts 2 PCI clock cycles. 10 1: The secondary discard timer counts 2 PCI clock cycles. If the secondary interface is in PCI-X mode, this bit is ignored. Reset to 0h. Primary Master Timeout Status 15 0: The primary discard timer counts 2 PCI clock cycles. 10 1: The primary discard timer counts 2 PCI clock cycles. If the primary interface is in PCI-X mode, this bit is ignored. Reset to 0h. Fast Back-to-Back Transaction Enable Designates PI7C21P100 does not generate fast back-to-back transactions. Returns 0 when read. Secondary Interface Reset 0: Does not force the assertion of S_RST# on the secondary interface 1: Forces the assertion of S_RST# on the secondary interface. Reset to 0h. Master Abort Mode 0: Do not report master aborts. Returns FFFFFFFFh on reads and discard data on writes. 1: Report master aborts by signaling target abort if possible or by asserting SERR# (if enabled). If in PCI-X mode, PI7C21P100 will return a split completion message, leaving the host bridge to return FFFFFFFFh on any nonposted transaction when the non-posted transaction ends in a master abort. Reset to 0h. Reserved. Returns 0 when read. VGA Enable 0: Does not forward VGA compatible memory and I/O addresses from the primary to secondary interface unless they are enabled for forwarding by the defined I/O and memory address ranges. 1: Forwards VGA compatible memory and I/O addresses from the primary to secondary interface (if the I/O enable and Memory enable bits are set) independent of the defined I/O and memory address ranges and independent of the ISA enable bit. ISA Enable 0: Forward downstream all I/O addresses in the address defined by the I/O base and limit registers. 1: Forward upstream all I/O addresses in the address range defined by the I/O base and limit registers that are in the first 64KB of PCI I/O address space Reset to 0h. S_SERR# Enable 0: Disable the forwarding of S_SERR# to P_SERR# 1: Enable the forwarding of S_SERR# to P_SERR#. Reset to 0h.
26
Master Timeout Status
RWC
25
Secondary Master Timeout Status
RW
24
Primary Master Timeout Status
RW
23 22
Fast Back-to-Back Secondary Interface Reset Master Abort Mode
RO RW
21
RW
20 19
RESERVED VGA Enable
RO RW
18
ISA Enable
RW
17
S_SERR# Enable
RW
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
BIT 16 FUNCTION Parity Error Response Enable TYPE RW DESCRIPTION Parity Error Response Enable 0: Ignore address and data parity errors on the secondary interface. 1: Enable parity error detection on the secondary interface.
8.1.34
PRIMARY DATA BUFFERING CONTROL REGISTER - OFFSET 40h
BIT 15 14:12 FUNCTION RESERVED Maximum Memory Read Byte Count TYPE RO RW DESCRIPTION Reserved. Returns 0h when read. Maximum Memory Read Byte Count 000: 512 bytes (default) 001: 128 bytes 010: 256 bytes 011: 512 bytes 100: 1024 bytes 101: 2048 bytes 110: 4096 bytes 111: 512 bytes Maximum byte count is used by PI7C21P100 when generating read requests on the secondary interface in response to a memory read operation initiated on the primary interface which is in PCI mode and bits[9:8], bits[7:6], or bits[5:4] are set to full prefetch. Reset to 000 Relaxed Ordering Enable 0: Relaxed ordering is disabled in conventional PCI mode. 1: At the primary interface, read completions that occur after the first read completion are allowed to bypass posted writes and complete with a higher priority in conventional PCI mode. In PCI-X mode, the relaxed ordering bit in the attribute field will take precedence. Reset to 0 Primary Special Delayed Read Mode Enable 0: Retry any primary master which repeats its transaction with command code changes. 1: Allows any primary master to change memory command code (MR, MRL, MRM) after it has received a retry. PI7C21P100 will complete the memory read transaction and return data back to the primary bus master if the address and byte enables are the same. This bit is ignored in PCI-X mode. Reset to 0 Primary Read Prefetch Mode 00: One cache line prefetch if memory read address is in the prefetchable range at the primary interface 01: Reserved 10: Full prefetch if memory read address is in the prefetchable range at the primary interface. 11: Disconnect on the first DWORD. These bits are ignored in PCI-X mode. Reset to 00 Primary Read Line Prefetch Mode 00: One cache line prefetch if memory read line address is in prefetchable range at the primary interace 01: Reserved 10: Full prefetch if memory read multiple address is in prefetchable range at the primary interface 11: Reserved. These bits are ignored if the primary interface is in PCI-X mode. Primary Read Multiple Prefetch Mode 00: One cache line prefetch if memory read multiple address is in prefetchable range at the primary interface. 01: Reserved. 10: Full prefetch if memory read multiple address is in prefetchable range at the primary interface. 11: Reserved. These bits are ignored if the primary interface is in PCI-X mode. Reset to 10. Reserved. Returns 0000 when read.
11
Enable Relaxed Ordering
RW
10
Primary Special Delayed Read Mode Enable
RW
9:8
Primary Read Prefetch Mode
RW
7:6
Primary Read Line Prefetch Mode
RW
5:4
Primary Read Multiple Prefetch Mode
RW
3:0
RESERVED
RO
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.35
SECONDARY DATA BUFFERING CONTROL REGISTER - OFFSET 40h
BIT 31 30.28 FUNCTION RESERVED Maximum Memory Read Byte Count TYPE RO RW DESCRIPTION Reserved. Returns 0h when read. Maximum Memory Read Byte Count 000: 512 bytes (default) 001: 128 bytes 010: 256 bytes 011: 512 bytes 100: 1024 bytes 101: 2048 bytes 110: 4096 bytes 111: 512 bytes Maximum byte count is used by PI7C21P100 when generating read requests on the primary interface in response to a memory read operation initiated on the secondary interface which is in conventional PCI mode and bits[9:8], bits[7:6], or bits[5:4] are set to full prefetch. Reset to 000 Relaxed Ordering Enable 0: Relaxed ordering is disabled in conventional PCI mode. 1: At the secondary interface, read completions that occur after the first read completion are allowed to bypass posted writes and complete with a higher priority in conventional PCI mode. In PCI-X mode, the relaxed ordering bit in the attribute field will take precedence. Reset to 0 Secondary Special Delayed Read Mode Enable 0: Retry any secondary master which repeats its transaction with command code changes. 1: Allows any secondary master to change memory command code (MR, MRL, MRM) after it has received a retry. PI7C21P100 will complete the memory read transaction and return data back to the primary bus master if the address and byte enables are the same. This bit is ignored in PCI-X mode. Reset to 0 Secondary Read Prefetch Mode 00: One cache line prefetch if memory read address is in the prefetchable range at the secondary interface 01: Reserved 10: Full prefetch if memory read address is in the prefetchable range at the secondary interface. 11: Disconnect on the first DWORD. These bits are ignored in PCI-X mode. Reset to 00 Secondary Read Line Prefetch Mode 00: One cache line prefetch if memory read line address is in prefetchable range at the secondary interface 01: Reserved 10: Full prefetch if memory read multiple address is in prefetchable range at the secondary interface 11: Reserved. These bits are ignored if the secondary interface is in PCI-X mode. Secondary Read Multiple Prefetch Mode 00: One cache line prefetch if memory read multiple address is in prefetchable range at the secondary interface. 01: Reserved. 10: Full prefetch if memory read multiple address is in prefetchable range at the secondary interface. 11: Reserved. These bits are ignored if the secondary interface is in PCI-X mode. Reset to 10. Reserved. Returns 0000 when read.
27
Enable Relaxed Ordering
RW
26
Secondary Special Delayed Read Mode Enable
RW
25:24
Secondary Read Prefetch Mode
RW
23:22
Secondary Read Line Prefetch Mode
RW
21:20
Secondary Read Multiple Prefetch Mode
RW
19:16
RESERVED
RO
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.36
MISCELLANEOUS CONTROL REGISTER - OFFSET 44h
BIT 7:3 2 FUNCTION RESERVED Primary Configuration Busy TYPE RO RW DESCRIPTION Reserved. Returns 00000 when read. Primary Configuration Busy 0: Type 0 configuration commands accepted normally on the primary interface. 1: Type 0 configuration commands retried on the primary interface. This bit can be read from both the primary and secondary buses, but written only from the secondary bus. Reset value is based on P_CFG_BUSY. If P_CFG_BUSY is tied HIGH, reset to 1. Data Parity Error Recovery Enable 0: All PI7C21P100 to pass parity errors through. 1: Cause SERR# to be asserted whenever either master-data-parityerror bit[8] is set. Reset to 1. Parity Error Behavior 0: PI7C21P100 will pass the corrupted data sequence and PERR# will be asserted (if enabled), but PI7C21P100 will not complete the data and CBE# for performing completion on the initiating bus when detecting a data parity error on a non-posted write transaction. 1: Transaction will be completed on the originating bus, PERR# will be asserted (if enabled), he appropriate status bits will be set, the data will be discarded and no request will be queued. Reset to 1.
1
Data Parity Error Recovery Enable
RW
0
Parity Error Behavior
RW
8.1.37
EXTENDED CHIP CONTROL REGISTER 1 - OFFSET 48h
BIT 7 6 FUNCTION RESERVED Bridge Disconnect Discard Timer TYPE RO RW DESCRIPTION Reserved. Returns 0 when read. Bridge Disconnect Discard Control 0: PI7C21P100 will discard remaining data after it disconnects the external master during burst memory reads transaction on the PCI source bus. 1: PI7C21P100 will keep remaining data after it disconnects the external master during burst memory reads on the PCI source bus, until the external master returns or the discard timer expires. Reset to 0. Memory Write Transaction Entry Control 0: PI7C21P100 can accept 4 memory write transactions 1: PI7C21P100 can accept 8 memory write transactions Reset to 0. Synchronous Mode Enable 0: Synchronous mode is disabled, and the asynchronous clock input is supported. 1: Synchronous mode is enabled and is used to decrease the frequency to frequency latency when PI7C21P100 is forwarding transactions through the bridge. The clock inputs have to be synchronized and the primary clock need to lead the secondary clock with the following combinations: Primary Secondary time 33MHz 33MHz 0 - 14ns 66MHz 66MHz 0 - 7ns 66MHz 33MHz 3 - 14ns 133MHz 133MHz 0 - 3ns 133MHz 66MHz 3 - 7ns Reset to 0 Upstream Memory Read Prefetching Dynamic Control 0: Enable upstream memory read prefetching dynamic control 1: Disable upstream memory read prefetching dynamic control Reset to 0 (Described in section 4.3.6)
5
Memory Write Transaction Entry Control Synchronous Mode Enable
RW
4
RW
3
Upstream Memory Read Prefetching Dynamic Control
RW
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
BIT 2 FUNCTION Downstream Memory Read Prefetching Dynamic Control RESERVED TYPE RW DESCRIPTION Downstream Memory Read Prefetching Dynamic Control 0: Enable downstream memory read prefetching dynamic control 1: Disable downstream memory read prefetching dynamic control Reset to 0 (Described in section 4.3.6) Reserved. Returns 00 when read.
1:0
RO
8.1.38
EXTENDED CHIP CONTROL REGISTER 2 - OFFSET 48h
BIT 11:10 FUNCTION Minimum Free Space in Memory Data FIFO Control (Secondary) TYPE RW DESCRIPTION Minimum Free Space in Memory Data FIFO Control (Secondary) Selects the minimum free space in the memory data FIFO to accept memory writes on the secondary bus in PCI-X mode 00: 128 bytes of free space to accept memory writes 01: 256 bytes of free space to accept memory writes 10: 512 bytes of free space to accept memory writes 11: 128 bytes of free space to accept memory writes Reset to 00 Minimum Free Space in Memory Data FIFO Control (Primary) Selects the minimum free space in the memory data FIFO to accept memory writes on the primary bus in PCI-X mode 00: 128 bytes of free space to accept memory writes 01: 256 bytes of free space to accept memory writes 10: 512 bytes of free space to accept memory writes 11: 128 bytes of free space to accept memory writes Reset to 00
9:8
Minimum Free Space in Memory Data FIFO Control (Primary)
RW
8.1.39
ARBITER MODE REGISTER - OFFSET 50h
BIT 15:8 FUNCTION Arbiter Fairness Counter TYPE RW DESCRIPTION Arbiter Fairness Counter These bits are the initialization value of a counter used by the internal arbiter. It controls the number of PCI bus cycles that the arbiter holds a device's PCI bus grant active after detecting a PCI bus request from another device. The counter is reloaded whenever a new PCI bus grant is asserted. For every new PCI bus grant, the counter is armed to decrement when it detects the de-assertion of FRAME#. If the arbiter fairness counter is set to 00h, the arbiter will not remove a device's PCI bus grant until the device has de-asserted its PCI bus request. Reset to 08h GNT# Output Toggling Enable 0: GNT# not de-asserted after granted master asserts FRAME# 1: GNT# de-asserts for 1 clock after 2 clocks from the granted master asserting FRAME#. Reset to 0 Broken Master Refresh 0: A broken master will be ignored forever except when it de-asserts its REQ# for at least 1 clock 1: Refresh broken master state after all other masters have been served once. Reset to 0 Reserved. Returns 0000 when read. Broken Master Timeout Enable 0: Broken master timeout disabled 1: Broken master timeout enabled. This enables the internal arbiter to count 16 PCI bus cycles while waiting for FRAME# to become active when a device's PCI bus GNT# is active and the PCI bus is idle. If the broken master timeout expires, the PCI bus GNT# for the device is de-asserted. Reset to 0
7
GNT# Output Toggling Enable
RW
6
Broken Master Refresh
RW
5:2 1
RESERVED Broken Master Timeout Enable
RO RW
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
BIT 0 FUNCTION External Arbiter TYPE RO DESCRIPTION External Arbiter 0: Enable internal arbiter. 1: Disable internal arbiter. Reset to 0 or 1 according to the value of S_ARB# during the reset. If S_ARB# is tied LOW, then returns 0 when read. If S_ARB# is tied HIGH, then returns 1 when read.
8.1.40
ARBITER ENABLE REGISTER - OFFSET 54h
BIT 7 6 FUNCTION RESERVED Enable Arbiter 6 TYPE RO RW DESCRIPTION Reserved. Returns 0 when read. Enable Arbiter 6 0: Disable arbitration for master 6 1: Enable arbitration for master 6 Reset to 1 Enable Arbiter 5 0: Disable arbitration for master 5 1: Enable arbitration for master 5 Reset to 1 Enable Arbiter 4 0: Disable arbitration for master 4 1: Enable arbitration for master 4 Reset to 1 Enable Arbiter 3 0: Disable arbitration for master 3 1: Enable arbitration for master 3 Reset to 1 Enable Arbiter 2 0: Disable arbitration for master 2 1: Enable arbitration for master 2 Reset to 1 Enable Arbiter 1 0: Disable arbitration for master 1 1: Enable arbitration for master 1 Reset to 1 Enable Arbiter 0 0: Disable arbitration for internal bridge request 1: Enable arbitration for internal bridge request Reset to 1
5
Enable Arbiter 5
RW
4
Enable Arbiter 4
RW
3
Enable Arbiter 3
RW
2
Enable Arbiter 2
RW
1
Enable Arbiter 1
RW
0
Enable Arbiter 0
RW
8.1.41
ARBITER PRIORITY REGISTER - OFFSET 58h
BIT 7 6 FUNCTION RESERVED Arbiter Priority 6 TYPE RO RW DESCRIPTION Reserved. Returns 0 when read. Arbiter Priority 6 0: Low priority request to master 6 1: High priority request to master 6 Reset to 0 Arbiter Priority 5 0: Low priority request to master 5 1: High priority request to master 5 Reset to 0 Arbiter Priority 4 0: Low priority request to master 4 1: High priority request to master 4 Reset to 0 Arbiter Priority 3 0: Low priority request to master 3 1: High priority request to master 3 Reset to 0
5
Arbiter Priority 5
RW
4
Arbiter Priority 4
RW
3
Arbiter Priority 3
RW
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
BIT 2 FUNCTION Arbiter Priority 2 TYPE RW DESCRIPTION Arbiter Priority 2 0: Low priority request to master 2 1: High priority request to master 2 Reset to 0 Arbiter Priority 1 0: Low priority request to master 1 1: High priority request to master 1 Reset to 0 Arbiter Priority 0 0: Low priority request to internal bridge 1: High priority request to internal bridge Reset to 1
1
Arbiter Priority 1
RW
0
Arbiter Priority 0
RW
8.1.42
SERR# DISABLE REGISTER - OFFSET 5Ch
BIT 7:5 4 FUNCTION RESERVED PERR# on Posted Writes SERR# Disable TYPE RO RW DESCRIPTION Reserved. Returns 000 when read. PERR# on Posted Writes SERR# Disable 0: Assert SERR# and set bit[30] offset 04h of the status register if bit[8] offset 04h in the command register is set. Discard the delayed transaction. 1: Disable the assertion of SERR#. Reset to 0 Primary Discard Timer SERR# Disable 0: Assert SERR# and update bit[30] offset 04h of the status register if the primary discard timer expires and bit[8] offset 04h in the command register is set and bit[27] offset 3Ch in the control register is set. Discard the delayed transaction and set bit[3] offset 6Ch of the retry and timer status register. 1: Disable the assertion of SERR# if the primary discard timer expires. Discard the delayed transaction and set bit[3] offset 6Ch of the retry and timer status register. Reset to 0 Secondary Discard Timer SERR# Disable 0: Assert SERR# and update bit[30] offset 04h of the status register if the secondary discard timer expires and bit[8] offset 04h in the command register is set and bit[27] offset 3Ch in the control register is set. Discard the delayed transaction and set bit[3] offset 6Ch of the retry and timer status register. 1: Disable the assertion of SERR# if the primary discard timer expires. Discard the delayed transaction and set bit[3] offset 6Ch of the retry and timer status register. Reset to 0 Primary Retry Count SERR# Disable 0: Assert SERR# and update bit[30] offset 04h of the status register if the primary retry counter expires and bit[8] offset 04h in the command register is set. Discard the transaction and set bit[1] offset 6Ch of the retry and timer status register. 1: Disable the assertion of SERR# if the primary retry counter expires. Discard the transaction and set bit[1] offset 6Ch of the retry and timer status register. Reset to 0 Secondary Retry Count SERR# Disable 0: Assert SERR# and update bit[30] offset 04h of the status register if the secondary retry counter expires and bit[8] offset 04h in the command register is set. Discard the transaction and set bit[0] offset 6Ch of the retry and timer status register. 1: Disable the assertion of SERR# if the primary retry counter expires. Discard the transaction and set bit[0] offset 6Ch of the retry and timer status register. Reset to 0
3
Primary Discard Timer SERR# Disable
RW
2
Secondary Discard Timer SERR# Disable
RW
1
Primary Retry Count SERR# Disable
RW
0
Secondary Retry Count SERR# Disable
RW
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.43
PRIMARY RETRY COUNTER REGISTER - OFFSET 60h
BIT 31 30:25 24 23:17 16 15:9 8 7:0 FUNCTION 2G Retry Count Control RESERVED 16M Retry Count Control RESERVED 64K Retry Count Control RESERVED 256 Retry Count Control RESERVED TYPE RW RO RW RO RW RO RW RO DESCRIPTION 2G Retry Count Control 1: Designates 2G retries before expiration Reset to 0 Reserved. Returns 000000 when read. 16M Retry Count Control 1: Designates 16M retries before expiration. Reset to 0 Reserved. Returns 0000000 when read. 64K Retry Count Control 1: Designates 64K retries before expiration. Reset to 0 Reserved. Returns 0000000 when read. 256 Retry Count Control 1: Designates 256 retries before expiration. Reset to 0 Reserved. Returns 00000000 when read.
The below settings are the only allowed values. Other settings are not valid and will result in smaller retry counts. When the counter expires, the bridge discards the requested transaction on the primary bus and issues SERR# on the primary bus if enabled. 0000 0000: 8000 0000: 0100 0000: 0001 0000: 0000 0100: No expiration limit Allow 2G retries before expiration Allow 16M retries before expiration Allow 64K retries before expiration Allow 256 retries before expiration
8.1.44
SECONDARY RETRY COUNTER REGISTER - OFFSET 64h
BIT 31 30:25 24 23:17 16 15:9 8 7:0 FUNCTION 2G Retry Count Control RESERVED 16M Retry Count Control RESERVED 64K Retry Count Control RESERVED 256 Retry Count Control RESERVED TYPE RW RO RW RO RW RO RW RO DESCRIPTION 2G Retry Count Control 1: Designates 2G retries before expiration Reset to 0 Reserved. Returns 000000 when read. 16M Retry Count Control 1: Designates 16M retries before expiration. Reset to 0 Reserved. Returns 0000000 when read. 64K Retry Count Control 1: Designates 64K retries before expiration. Reset to 0 Reserved. Returns 0000000 when read. 256 Retry Count Control 1: Designates 256 retries before expiration. Reset to 0 Reserved. Returns 00000000 when read.
The below settings are the only allowed values. Other settings are not valid and will result in smaller retry counts. When the counter expires, the bridge discards the requested transaction on the secondary bus and issues SERR# on the primary bus if enabled. 0000 0000: 8000 0000: 0100 0000: 0001 0000: 0000 0100: No expiration limit Allow 2G retries before expiration Allow 16M retries before expiration Allow 64K retries before expiration Allow 256 retries before expiration
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.45
DISCARD TIMER CONTROL REGISTER - OFFSET 68h
BIT 7:4 3 FUNCTION RESERVED Primary Discard Timer Short Duration TYPE RO RW DESCRIPTION Reserved. Returns 0000 when read. Primary Discard Timer Short Duration 0: Use bit[24] offset 3Ch of the bridge control register to indicate how many PCI clocks should be allowed before the primary discard timer expires. 1: 64 PCI clocks allowed before the discard time expires. Reset to 0 Secondary Discard Timer Short Duration 0: Use bit[25] offset 3Ch of the bridge control register to indicate how many PCI clocks should be allowed before the secondary discard timer expires. 1: 64 PCI clocks allowed before the secondary discard timer expires. Reset to 0 Primary Discard Timer Disable 0: Enable the primary discard timer in conjunction with bit[27] offset 3Ch of the bridge control register 1: Disable the primary discard timer in conjunction with bit[27] offset 3Ch of the bridge control register Reset to 0 Secondary Discard Timer Disable 0: Enable the secondary discard timer in conjunction with bit[27] offset 3Ch of the bridge control register 1: Disable the secondary discard timer in conjunction with bit[27] offset 3Ch of the bridge control register Reset to 0
2
Secondary Discard Timer Short Duration
RW
1
Primary Discard Timer Disable
RW
0
Secondary Discard Timer Disable
RW
8.1.46
RETRY AND TIMER STATUS REGISTER - OFFSET 6Ch
BIT 7:4 3 FUNCTION RESERVED Primary Discard Timer Status Secondary Discard Timer Status Primary Retry Counter Status Secondary Retry Counter Status TYPE RO RW DESCRIPTION Reserved. Returns 0000 when read. Primary Discard Timer Status 0: The primary discard timer has not expired since the last reset. 1: The primary discard timer has expired since the last reset. Reset to 0 Secondary Discard Timer Status 0: The secondary discard timer has not expired since the last reset. 1: The secondary discard timer has expired since the last reset. Reset to 0 Primary Retry Counter Status 0: The primary retry counter has not expired since the last request. 1: The primary retry counter has expired since the last request. Reset to 0. Secondary Retry Counter Status 0: The secondary retry counter has not expired since the last request. 1: The secondary retry counter has expired since the last request. Reset to 0.
2
RW
1
RW
0
RW
8.1.47
OPAQUE MEMORY ENABLE REGISTER - OFFSET 70h
BIT 7:1 0 FUNCTION RESERVED Opaque Memory Enable TYPE RO RW DESCRIPTION Reserved. Returns 0000000 when read. Opaque Memory Enable 0: Disable the opaque memory address range if OPAQUE_EN=0. 1: Enable the opaque memory address range if OPAQUE_EN=1. Reset to the value of OPAQUE_EN during reset.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.48
OPAQUE MEMORY BASE REGISTER - OFFSET 74h
BIT 15:4 FUNCTION Opaque Memory Base Address TYPE RW DESCRIPTION Opaque Memory Base Address Address bits[31:20] of the opaque memory base address in conjunction with the opaque memory base upper 32-bit register and opaque memory limit address. In this range, memory transactions are not accepted by PI7C21P100 on both primary and secondary interfaces. Reset to 000h Address Select Returns 0001 when read to indicate 64-bit addressing.
3:0
Address Select
RO
8.1.49
OPAQUE MEMORY LIMIT REGISTER - OFFSET 74h
BIT 31:20 FUNCTION Opaque Memory Limit Address TYPE RW DESCRIPTION Opaque Memory Limit Address Address bits[31:20] of the opaque memory limit address in conjunction with the opaque memory limit upper 32-bit register and opaque memory base address. In this range, memory transactions are not accepted by PI7C21P100 on both primary and secondary interfaces. Reset to FFFh Address Select Returns 0001 when read to indicate 64-bit addressing.
19:16
Address Select
RO
8.1.50
OPAQUE MEMORY BASE UPPER 32-BIT REGISTER - OFFSET 78h
BIT 31:0 FUNCTION Opaque Memory Base Upper 32-bit Register TYPE RW DESCRIPTION Opaque Memory Base Upper 32-bit Register Address bits[63:32] of the opaque memory base address. In this range, memory transactions are not accepted by PI7C21P100 on both primary and secondary interfaces. Reset to FFFF FFFFh
8.1.51
OPAQUE MEMORY LIMIT UPPER 32-BIT REGISTER - OFFSET 7Ch
BIT 31:0 FUNCTION Opaque Memory Base Upper 32-bit Register TYPE RW DESCRIPTION Opaque Memory Base Upper 32-bit Register Address bits[63:32] of the opaque memory limit address. In this range, memory transactions are not accepted by PI7C21P100 on both primary and secondary interfaces. Reset to FFFF FFFFh
8.1.52
PCI-X CAPABILITY ID REGISTER - OFFSET 80h
BIT 7:0 FUNCTION PCI-X Capability ID TYPE RO DESCRIPTION PCI-X Capability ID Returns 07h when read to indicate that this register set of the Capabilities List is a PCI-X register set.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.53
NEXT CAPABILITY POINTER REGISTER - OFFSET 80h
BIT 15:8 FUNCTION Next Capability Pointer TYPE RO DESCRIPTION Next Capability Pointer Returns 90h when read to indicate that there are more list items in the Capabilities List.
8.1.54
PCI-X SECONDARY STATUS REGISTER - OFFSET 80h
BIT 31:25 24:22 FUNCTION RESERVED Secondary Clock Frequency TYPE RO RO DESCRIPTION Reserved. Returns 0000000 when read. Secondary Clock Frequency Enables the configuration software to determine what mode and what frequency PI7C21P100 set the secondary bus to the last time the secondary RST# was asserted. VALUE MAX CLOCK FREQUENCY MIN CLK PERIOD 000 conventional mode N/A 001 66 MHz 15ns 010 100 MHz 10ns 011 133 MHz 7.5ns 1xx Reserved Reserved Split Request Delayed 0: The bridge has not delayed a split request 1: The bridge has delayed a split request because the bridge cannot forward a transaction to the secondary bus because there isn't enough room within the limit specified in the split transaction commitment limit field in the downstream split transaction control register. Reset to 0 Split Completion Overrun 0: PI7C21P100 has accepted all split completions. 1: PI7C21P100 has terminated a split completion on the secondary bus with retry or disconnect at the next ADB because the bridge buffers were full. Reset to 0 Unexpected Split Completion 0: No unexpected split completion has been received. 1: An unexpected split completion has been received with the requested ID equal to the bridge's secondary bus number, device number 00h, and function number 0 on the bridge secondary interface. Reset to 0 Split Completion Discarded 0: No split completion has been discarded. 1: A split completion moving toward the secondary bus has been discarded by the bridge because the requester would not accept it. Reset to 0. 133MHz Capable Returns 1 when read to indicate PI7C21P100 is capable of 133MHz operation on the secondary interface. 64-bit Device Returns a 1 when the AD interface is 64-bits wide on the secondary bus and 64BIT_DEV#=1. Returns a 0 when 64BIT_DEV#=0.
21
Split Request Delayed
RW
20
Split Completion Overrun
RW
19
Unexpected Split Completion
RW
18
Split Completion Discarded
RW
17 16
133MHz Capable 64-bit Device
RO RO
8.1.55
PCI-X BRIDGE PRIMARY STATUS REGISTER - OFFSET 84h
BIT 31:22 FUNCTION RESERVED TYPE RO DESCRIPTION Reserved. Returns 00000000 when read.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
BIT 21 FUNCTION Split Request Delayed TYPE RW DESCRIPTION Split Request Delayed 0: PI7C21P100 has not delayed a split request. 1: A split request moving toward the primary bus has been delayed by PI7C21P100 because there is not enough room within the limit specified in the split transaction commitment limit field in the upstream split transaction control register. Reset to 0 Split Completion Overrun 0: PI7C21P100 has accepted all split completions. 1: PI7C21P100 has terminated a split completion on the primary bus with retry or disconnect at the next ADB because the buffers in the bridge were full. Reset to 0 Unexpected Split Completion 0: No unexpected split completion has been received. 1: An unexpected split completion has been received with the requested ID equal to the bridge's primary bus number, device number, and function number on the bridge pirmary interface. Reset to 0 Split Completion Discarded 0: No split completion has been discarded. 1: A split completion moving toward the primary bus has been discarded by the bridge because the requester would not accept it. Reset to 0. 133MHz Capable Returns 1 when read to indicate PI7C21P100 is capable of 133MHz operation on the primary interface. 64-bit Device Returns a 1 when the AD interface is 64-bits wide on the primary bus and P_REQ64#=0 at P_RST# de-assertion. Otherwise, AD interface is 32-bits wide. Bus Number This is an additional address from which the contents of the primary bus number register on type 1 configuration space header is read. The bridge uses the bus number, device number, and function number fields to create the completer ID when responding with a split completion to a read of an internal bridge register. These fields are also used for cases when one interface is in conventional PCI mode and the other is in PCI-X mode. Reset to 11111111 Device Number The device number (AD[15:11]) of a type 0 configuration transaction is assigned to the bridge by the connection of system hardware. Each time the bridge is addressed by a configuration write transaction, the bridge updates this register with the contents of AD[15:11] of the address phase of the configuration transaction, regardless of which register in the bridge is addressed by the transaction. The bridge is addressed by a configuration write transaction if all of the following are true: - The transaction uses a configuration write command - IDSEL is asserted during the address phase - AD[1:0] are 00 (type 0 configuration transaction) - AD[10:8] of the configuration address contain the appropriate function number Reset to 11111 Function Number The function number (AD[10:8]) of the address of a type 0 configuration transaction to which the bridge responds. Reset to 000
20
Split Completion Overrun
RW
19
Unexpected Split Completion
RW
18
Split Completion Discarded
RW
17 16
133MHz Capable 64-bit Device
RO RO
15:8
Bus Number
RO
7:3
Device Number
RO
2:0
Function Number
RO
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8.1.56
SECONDARY BUS UPSTREAM SPLIT TRANSACTION REGISTER - OFFSET 88h
BIT 31:16 FUNCTION Split Transaction Commitment Limit TYPE RW DESCRIPTION Split Transaction Commitment Limit This field indicates the cumulative sequence size of the commitment limit in units of ADQ's. Software is allowed to program this field to any value greater than or equal to the contents of the split transaction capacity field. For example, if the limit is set to FFFFh, the bridge is allowed to forward all split requests of any size regardless of the amount of buffer space available. If the limit is set to 0100h or greater, causes the bridge to forward accepted split requests of any size regardless of the amount of buffer space available. The limit can be programmed at any time after reset. The value of the limit is equal to the split transaction capacity field reset. Reset to 0020h Split Transaction Capability The bridge returns 0020h to indicate that there are 32 ADQ's (4K bytes) available buffer space for storing split completions for memory reads. This applies to requesters on the secondary bus addressing completers on the primary bus. Reset to 0020h
15:0
Split Transaction Capability
RO
8.1.57
PRIMARY BUS DOWNSTREAM SPLIT TRANSACTION REGISTER - OFFSET 8Ch
BIT 31:16 FUNCTION Split Transaction Commitment Limit TYPE RW DESCRIPTION Split Transaction Commitment Limit This field indicates the cumulative sequence size of the commitment limit in units of ADQ's. Software is allowed to program this field to any value greater than or equal to the contents of the split transaction capacity field. For example, if the limit is set to FFFFh, the bridge is allowed to forward all split requests of any size regardless of the amount of buffer space available. If the limit is set to 0100h or greater, the bridge will forward accepted split requests of any size regardless of the amount of buffer space available. The limit can be programmed at any time after reset. The value of the limit is equal to the split transaction capacity field reset. Reset to 0020h Split Transaction Capability The bridge returns 0020h to indicate that there are 32 ADQ's (4K bytes) available buffer space for storing split completions for memory reads. This applies to requesters on the secondary bus addressing completers on the primary bus. Reset to 0020h
15:0
Split Transaction Capability
RO
8.1.58
POWER MANAGEMENT ID REGISTER - OFFSET 90h
BIT 7:0 FUNCTION Power Management ID TYPE RO DESCRIPTION Power Management ID Returns 01h when read indicating that this register set of the capabilities list is a power management register set.
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
8.1.59
NEXT CAPABILITIES POINTER REGISTER - OFFSET 90h
BIT 15:8 FUNCTION Next Capabilities Pointer TYPE RO DESCRIPTION Next Capabilities Pointer Returns 00h when read indicating that there are no more list items in the capabilities list.
8.1.60
POWER MANAGEMENT CAPABILITIES REGISTER - OFFSET 90h
BIT 31:27 26 25 24:22 FUNCTION PME# Pin Support D2 Power State Support D1 Power State Support AUX Current TYPE RO RO RO RO DESCRIPTION PME# Pin Support Returns 00000 when read designating that PI7C21P100 does not support the PME# pin. D2 Power State Support Returns 0 when read indicating the D2 power management state is not supported. D1 Power State Support Returns 0 when read indicating the D1 power management state is not supported. AUX Current Returns 000 when read indicating PME# generation is not supported in the D3cold power management state. Device Specific Initialization Returns 0 when read indicating that no special initialization of this function beyond the standard PCI configuration header is required following transition to the D0 un-initialized state. Reserved. Returns 0 when read. PME Clock Returns 0 when read indicating PME# generation is not supported. Version Returns 010 when read indicating PI7C21P100 complies with revision 2.0 of the PCI Power Management Interface Specification.
21
Device Specific Initialization RESERVED PME Clock Version
RO
20 19 18:16
RO RO RO
8.1.61
POWER MANAGEMENT CONTROL AND STATUS REGISTER - OFFSET 94h
BIT 15 14:13 12:9 8 7:2 FUNCTION PME Status Data Scale Data Select PME Enable RESERVED TYPE RO RO RO RO RO DESCRIPTION PME Status Returns 0 when read indicating PI7C21P100 does not support the PME# pin. Data Scale Returns 00 when read indicating the data register is not implemented. Data Select Returns 0000 when read indicating the data register is not implemented. PME Enable Returns 0 when read indication PME# generation is not supported. Reserved. Returns 000000 when read.
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BIT 1:0 FUNCTION Power State TYPE RW DESCRIPTION Power State Determines and reflects the current power state. If an unimplemented power state is written to this register, the bridge completes the write transaction, ignores the write data, and does not change the value of this field. Writing a value of D0 when the previous state was D3 will cause a device reset to occur without activating the secondary S_RST#. 00 01 10 11 Reset to 00 D0 D1 (not supported) D2 (not supported) D3
8.1.62
PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER - OFFSET 94h
BIT 31:24 23 FUNCTION Data Register Bus Power / Clock Control B2/B3 Support for D3HOT RESERVED TYPE RO RO DESCRIPTION Data Register Returns 0 when read indicating the data register is not implemented. Bus Power / Clock Control Returns 0 when read indicating the bus power / clock control is disabled and the secondary clock cannot be controlled by PI7C21P100. B2/B3 Support for D3HOT Returns 0 when read indicating B2/B3 support for D3HOT power management state is disabled. Reserved. Returns 000000 when read.
22
RO
21:16
RO
8.1.63
SECONDARY BUS PRIVATE DEVICE MASK REGISTER - OFFSET B0h
BIT 31:30 29 FUNCTION RESERVED Private Device Mask 13 TYPE RW RW DESCRIPTION Reserved. Returns 00 when read. Private Device Mast 13 0: Rerouting disabled for device 13 1: Block assertion of S_AD[29] for configuration transactions to device 13 and assert S_AD[31] instead. Reserved. Returns 000 when read. Private Device Mask 9 0: Rerouting disabled for device 9 1: Block assertion of S_AD[25] for configuration transactions to device 9 and assert S_AD[31] instead. Reserved. Returns 0 when read. Private Device Mask 7 0: Rerouting disabled for device 7 1: Block assertion of S_AD[23] for configuration transactions to device 7 and assert S_AD[31] instead. Private Device Mask 6 0: Rerouting disabled for device 6 1: Block assertion of S_AD[22] for configuration transactions to device 6 and assert S_AD[31] instead. Private Device Mask 5 0: Rerouting disabled for device 5 1: Block assertion of S_AD[21] for configuration transactions to device 5 and assert S_AD[31] instead.
28:26 25
RESERVED Private Device Mask 9
RW RW
24 23
RESERVED Private Device Mask 7
RW RW
22
Private Device Mask 6
RW
21
Private Device Mask 5
RW
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
BIT 20 FUNCTION Private Device Mask 4 TYPE RW DESCRIPTION Private Device Mask 4 0: Rerouting disabled for device 4 1: Block assertion of S_AD[20] for configuration transactions to device 4 and assert S_AD[31] instead. Reserved. Returns 00 when read. Private Device Mask 1 0: Rerouting disabled for device 1 1: Block assertion of S_AD[17] for configuration transactions to device 1 and assert S_AD[31] instead. Reserved. Returns 000000000000000000 when read.
19:18 17
RESERVED Private Device Mask 1
RW RW
16:0
RESERVED
RW
8.1.64
MISCELLANEOUS CONTROL REGISTER 2 - OFFSET B8h
BIT 15 14:10 9 FUNCTION Short Term Caching RESERVED Primary Prefetching Persistence Control TYPE RW RO RW DESCRIPTION Short Term Caching 0: Short term caching is disabled 1: Short term caching is enabled. Reserved. Returns 00000 when read. Primary Prefetching Persistence Control 0: PI7C21P100 discontinue prefetching on the secondary bus when the target disconnects, regardless of how much data has been buffered 1: PI7C21P100 continues prefetching on the secondary bus despite target disconnects until either the byte count specified by Primary Data Buffering Control Register has been prefetched, or the initiator disconnects. Secondary Prefetching Persistence Control 0: PI7C21P100 discontinue prefetching on the primary bus when the target disconnects, regardless of how much data has been buffered 1: PI7C21P100 continues prefetching on the primary bus despite target disconnects until either the byte count specified by Primary Data Buffering Control Register has been prefetched, or the initiator disconnects. Reserved. Returns 00h when read.
8
Secondary Prefetching Persistence Control
RW
7:0
RESERVED
RO
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
9
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support boundary scan in PI721P100 for board-level continuity test and diagnostics. The TAP pins assigned are TCK, TDI, TDO, TMS and TRST#. All digital input, output, input/output pins are tested except TAP pins. The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers including Bypass and Boundary Scan registers. The TAP controller is a synchronous 16-state machine driven by the Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to ensure the machine is in TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not active when the PCI resource is operating PCI bus cycles.
9.1
INSTRUCTION REGISTER
PI7C21P100 implements a 4-bit Instruction register to control the operation of the JTAG logic. The defined instruction codes are shown in. Those bit combinations that are not listed are equivalent to the BYPASS (1111) instruction:
Instruction EXTEST SAMPLE HIGHZ IDCODE BYPASS INT_SCAN Operation Code (binary) 0000 0100 0101 0110 1111 0010 Register Selected Boundary Scan Boundary Scan Bypass Device ID Bypass Internal Scan Operation Drives / receives off-chip test data Samples inputs / pre-loads outputs Tri-states outputs Accesses the Device ID register, to read manufacturer ID, part number, and version number Selected Bypass Register Scan test
9.2
BYPASS REGISTER
The required bypass register, a one-bit shift register, provides the shortest path between TDI and TDO when a bypass instruction is in effect. This allows rapid movement of test data to and from other components on the board. This path can be selected when no test operation is being performed on the PI7C21P100.
9.3
DEVICE ID REGISTER
This register identifies Pericom as the manufacturer of the device and details the part number and revision number for the device.
BIT 31:28 27:12 11:0 TYPE RO RO RO VALUE 0h 01A7h 47Fh DESCRIPTION Version number Last 4 digits (hex) of the die part number Pericom identifier assigned by JEDEC Bit 0 is set to 1
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9.4
BOUNDARY SCAN REGISTER
The boundary scan register is a required set of serial-shiftable register cells, formed by connecting boundary scan cells placed at the device's signal pins into a shift register path. The VDD, VSS, and JTAG pins are NOT in the boundary-scan chain. The input to the shift register is TDI and the output from the shift register is TDO. There are 4 different types of boundary scan cells, based on the function of each signal pin. The boundary scan register cells are dedicated logic and do not have any system function. Data may be loaded into the boundary-scan register master cells from the device input pins and output pin-drivers in parallel by the mandatory SAMPLE and EXTEST instructions. Parallel loading takes place on the rising edge of TCK.
9.5
JTAG BOUNDARY REGISTER ORDER
Table 9-1 JTAG BOUNDARY SCAN REGISTER
Boundary Scan Register Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name P_ACK64# P_AD[0] P_AD[1] P_AD[2] P_AD[3] P_AD[4] P_AD[5] P_AD[6] P_AD[7] P_AD[8] P_AD[9] P_AD[10] P_AD[11] P_AD[12] P_AD[13] P_AD[14] P_AD[15] P_AD[16] P_AD[17] P_AD[18] P_AD[19] P_AD[20] P_AD[21] P_AD[22] P_AD[23] P_AD[24] P_AD[25] P_AD[26] P_AD[27] P_AD[28] P_AD[29] P_AD[30] P_AD[31] Ball Location A2 B13 C13 B14 C15 A19 B16 C16 A20 B17 C17 C19 D18 F22 F20 G22 B20 G21 H22 H21 J22 J21 K22 D23 K21 E23 K20 G23 L22 L21 M22 M21 J23 Type BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR Tri-state Control Cell 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
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Boundary Scan Register Number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Pin Name P_AD[32] P_AD[33] P_AD[34] P_AD[35] P_AD[36] P_AD[37] P_AD[38] P_AD[39] P_AD[40] P_AD[41] P_AD[42] P_AD[43] P_AD[44] P_AD[45] P_AD[46] P_AD[47] P_AD[48] P_AD[49] P_AD[50] P_AD[51] P_AD[52] P_AD[53] P_AD[54] P_AD[55] P_AD[56] P_AD[57] P_AD[58] P_AD[59] P_AD[60] P_AD[61] P_AD[62] P_AD[63] P_CBE[0] P_CBE[1] P_CBE[2] P_CBE[3] P_CBE[4] P_CBE[5] P_CBE[6] P_CBE[7] P_CLK P_DEVSEL P_FRAME P_GNT P_IDSEL P_IRDY P_LOCK P_DRVR P_PAR P_PAR64 P_CFG_BUSY P_PERR
Ball Location L1 J1 J2 H1 G1 J3 E1 H2 H3 G3 F2 B1 F3 E3 F4 D2 C2 B5 B6 D6 B7 C7 B3 B8 A3 B9 C9 B10 A4 C10 D10 B11 A13 B18 D14 A15 A5 C11 B12 A7 E21 D21 A17 C20 B19 A16 C14 E2 C18 A9 C6 C8
Type BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR INPUT BIDIR BIDIR INPUT INPUT BIDIR INPUT INPUT BIDIR BIDIR INPUT BIDIR
Tri-state Control Cell 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
Boundary Scan Register Number 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136
Pin Name P_REQ64 P_REQ P_RST P_SERR P_STOP P_TRDY S_ACK64 S_AD[0] S_AD[1] S_AD[2] S_AD[3] S_AD[4] S_AD[5] S_AD[6] S_AD[7] S_AD[8] S_AD[9] S_AD[10] S_AD[11] S_AD[12] S_AD[13] S_AD[14] S_AD[15] S_AD[16] S_AD[17] S_AD[18] S_AD[19] S_AD[20] S_AD[21] S_AD[22] S_AD[23] S_AD[24] S_AD[25] S_AD[26] S_AD[27] S_AD[28] S_AD[29] S_AD[30] S_AD[31] S_AD[32] S_AD[33] S_AD[34] S_AD[35] S_AD[36] S_AD[37] S_AD[38] S_AD[39] S_AD[40] S_AD[41] S_AD[42] S_AD[43] S_AD[44]
Ball Location C12 B21 R3 B4 C4 B15 AA8 AA9 AB9 AC9 AC11 AB11 AC15 AA12 AA13 AC17 AB15 AA16 Y18 AB18 AA20 V20 W21 V21 V22 U21 U22 T22 W23 R21 T23 R22 N23 P20 M23 P21 P22 N21 N22 K4 K3 K2 L3 L2 R1 M3 M2 N3 N2 U1 P4 W1
Type BIDIR OUTPUT INPUT OUTPUT BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR
Tri-state Control Cell 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
Boundary Scan Register Number 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188
Pin Name S_AD[45] S_AD[46] S_AD[47] S_AD[48] S_AD[49] S_AD[50] S_AD[51] S_AD[52] S_AD[53] S_AD[54] S_AD[55] S_AD[56] S_AD[57] S_AD[58] S_AD[59] S_AD[60] S_AD[61] S_AD[62] S_AD[63] S_CBE[0] S_CBE[1] S_CBE[2] S_CBE[3] S_CBE[4] S_CBE[5] S_CBE[6] S_CBE[7] S_CLK S_CLK_STABLE S_DEVSEL S_FRAME S_GNT[1] S_GNT[2] S_GNT[3] S_GNT[4] S_GNT[5] S_GNT[6] S_ARB S_IRDY S_LOCK S_DRVR S_PAR S_PAR64 S_PCIXCAP S_PCIXCAP_PU S_PERR S_REQ[1] S_REQ[2] S_REQ[3] S_REQ[4] S_REQ[5] S_REQ64
Ball Location P3 Y1 P2 R3 R2 T3 T2 U3 U2 V4 V2 Y3 Y6 AA5 AA6 AB6 AA7 AB7 AB8 AB12 AB16 AB14 AA15 AC8 AA11 AB10 Y10 AB23 W3 AC21 AA14 AA19 AB1 Y2 AC5 AB4 AC4 T21 AC19 AC20 AC7 AA17 AA10 R23 AA1 AB17 AA23 AA2 W2 AB3 AB5 AB13
Type BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR INPUT INPUT BIDIR BIDIR OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT BIDIR BIDIR INPUT BIDIR BIDIR INPUT OUTPUT BIDIR INPUT INPUT INPUT INPUT INPUT INPUT
Tri-state Control Cell 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 202 203 204 205 206 207 367 368 369 370 376 371 372
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Boundary Scan Register Number 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
Pin Name S_REQ[6] S_RST S_SEL100 S_SERR S_STOP S_TRDY BAR_EN RESERVED XCLK_OUT S_IDSEL 64BIT_DEV IDSEL_ROUTE OPAQUE_EN -
Ball Location AC3 U23 V3 AB19 AB20 Y14 G2 D1 D3 AA22 Y22 AC22 AA18 -
Type INPUT OUTPUT INPUT INPUT BIDIR BIDIR INPUT INPUT OUTPUT INPUT INPUT INPUT CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL
Tri-state Control Cell 373 374 375 -
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Boundary Scan Register Number 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292
Pin Name -
Ball Location -
Type CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL
Tri-state Control Cell -
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Boundary Scan Register Number 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344
Pin Name -
Ball Location -
Type CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL
Tri-state Control Cell -
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
Boundary Scan Register Number 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376
Pin Name -
Ball Location -
Type CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL
Tri-state Control Cell -
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
10
10.1
ELECTRICAL INFORMATION
MAXIMUM RATINGS
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
SYMBOL VDD VDD2 VIN VOUT TA TJ TSTG PWC IOUT PARAMETER Core logic power supply I/O power supply voltage Input voltage Output voltage Ambient operating temperature Maximum junction temperature Storage temperature Worst case power dissipation Short circuit output current RATING TBD TBD TBD TBD 0 to 70 125 -55 to 125 TBD TBD UNITS V V V V C C C W mA
10.2
DC SPECIFICATIONS
SYMBOL VDD VDD2 VIH VIL CIN PARAMETER Core logic power supply I/O power supply voltage Input High voltage Input Low voltage Input pin capacitance min 2.3 3.0 2.0 -0.3 RATING typ 2.5 3.3 max 2.7 3.6 VDDI* + 0.5 0.3 VDDI* 8.0 UNITS V V V V pF
* VDDI is in reference to the power supply of the input device.
10.3
AC SPECIFICATIONS
Figure 10-1 PCI SIGNAL TIMING MEASUREMENTS
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
Table 10-1 AC TIMING SPECIFICATIONS PCI-X MODE
Symbol Tsu Tsu(ptp) Th Tval Tval(ptp) Ton Toff Parameter Input setup time to CLK - bussed signals Input setup time to CLK - point-topoint signals Input signal hold time from CLK CLK to signal valid delay - bussed signals CLK to signal valid delay - pointto-point signals Float to active delay Active to float delay PCI-X 133 min max 1.2 1.2 0.5 0.7 0.7 0 3.8 3.8 7 PCI-X 100 min max 1.2 1.2 0.5 0.7 0.7 0 3.8 3.8 7 min PCI-X 66 max 3.8 3.8 7 Units ns ns ns ns ns ns ns
1.7 1.7 0.5 0.7 0.7 0 -
Table 10-2 AC TIMING SPECIFICATIONS CONVENTIONAL PCI MODE
Symbol Tsu Tsu(ptp) Th Tval Tval(ptp) Ton Toff Parameter Input setup time to CLK - bussed signals Input setup time to CLK - point-topoint signals Input signal hold time from CLK CLK to signal valid delay - bussed signals CLK to signal valid delay - pointto-point signals Float to active delay Active to float delay PCI 66 min 3 5 0 2 2 2 max 6 6 14 min 7 10, 12 0 2 2 2 PCI 33 max 11 12 14 Units ns ns ns ns ns ns ns
10.4
POWER CONSUMPTION
PARAMETER Power dissipation for VDD (2.5V) Power dissipation for VDD2 (3.3V) *Running at 133MHz min RATING typ 1.33 0.46 max UNITS W W
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
11
MECHANICAL INFORMATION
Figure 11-1 PACKAGE DIAGRAM 31 X 31mm 304-PIN CSBGA
12
ORDERING INFORMATION
PART NUMBER PI7C21P100NH PI7C21P100NH SPEED 133MHz 133MHz PIN - PACKAGE 304-PINS - CSGA Pb-free & Green, 304-PINS - CSBGA TEMPERATURE 0C TO 85C 0C TO 85C
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PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION
NOTES:
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